My name is Uzair and I am a third year Electrical and Electronics Engineering student. Today marks the 6th official day since I began my internship at Aeste. Coming from an engineering background, I was given study material that took about 6 weeks to complete prior to the commencement of my internship. Yet still, from my very first day of office, I could tell that I have a long way to go and far too much to learn before I Read more
While there are a lot of examples that describe how to set up a LVM cache on an SSD for a HDD backed storage, they mostly fail to describe an additional step needed to preserve the cache across a reboot on a Ubuntu system. The culprit is that the drivers needed to enable the LVM cache are not built into the kernel, nor available in the initrd. Therefore, these drivers need to be added to the initrd. Additionally, some cache Read more
I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. This week, I have completed integrating the K3rangka with S3padu from the synthesis to bit generation to bram data replacement, writing a function similar to icebram that would replace the hexadecimal contents of the ecp5 bram, and finding a way to initialize the bram contents during synthesis so that the software for the fpga could be Read more
We have been running a thin-client setup in the office for a number of years now as we’ve found them to be easier to maintain, and it allowed everyone to login on any PC and access their work. Our thin-clients were all desktop PC-based machines with Gigabit Ethernet and no storage. However, the machines are getting old (some were close to a decade old) and were starting to show signs of age. So, we had to get some replacements and Read more
This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE flow). All flows are able to retrieve a Verilog file, a constraints file for determining the pinouts of the design, and additional arguments to generate a single bit file ready Read more
At the end of this week, I was able to speak with my supervisor to discuss my progress, mistakes, and next steps. During this discussion, we talked about the importance of representing a product in an understandable and simple manner in engineering, and I thought this was noteworthy. As this is my first time being in a working environment, I feel like I am starting to learn what it means to be in the producer’s shoes instead of the consumer, Read more
This week’s work was focused on writing the code to operate the design flow tools for the Xilinx 7 series, Intel Cyclone V, and Lattice ECP5. I had to gather all the tools I have found during the first few weeks of internship and integrated it into the K3rangka code. One main challenge to writing the code was to become familiar with the external library, Poco. My supervisor told me to operate the tools using only functions of Poco without Read more
I have finally begun making changes to the K3rangka code, trying to isolate the implementations of running yosys, nextpnr, and other tools into separate classes. Previously, the implementation was within the resource file that handles the HTTP requests. The implementation handled different type of FPGAs through if statements, which was possible for the ice40 and ecp5 due to their similarities in the open-source design flow. However, the implementation would be very different for the Xilinx 7 series and the Cyclone Read more
My search for the tools in Vivado and Quartus has come to an end. After three days of unsuccessful attempts to track down the processes while running Vivado and find the tools for each part of the design flow, I have given up and decided to resort to tcl commands which is well documented and also suggested on the yosys wiki page. The Vivado processes had dependencies such as libraries to be preloaded or variables of paths to be specified, Read more
This week, I was focused on finding tools for FPGA boards besides the Ice40 (Lattice ECP5, Xilinx Series 7, and Intel Cyclone V). My starting point was my supervisor’s suggestion to look at project Trellis, X-Ray, and Mistral for each of the boards respectively. Out of the three projects, project Trellis seemed to have the most progress as it was able to support a full design flow from Yosys to nextpnr to bitstream generation using a tool named ‘ecppack’. However, Read more