Engineering Elegance

C++11 Regular Expressions

Part of our project requires the use of regular expressions, which are now a part of the C++11 standard. However, getting things working was not completely straight-forward. All our development machines are running Ubuntu 14.04 LTS and we are using CLANG as our default compiler. Every C++11 regular expression example compiles perfectly using: $ clang++ -std=c++11 regexp.cc However, running the program inadvertently results in it crashing each and every time with the following error. terminate called after throwing an instance Read more

By Shawn, ago

Generic Automated Test Bench

The ultimate future goal is to create a generic Automated Test Bench that can be used with any of our IO cores. Of course the test vectors testing each core has to be different. However, since all our cores use wishbone bus this simplifies creating a generic solution. In this final post, I’ll list down the possible problems with creating a generic test bench and propose a solution for each one of them. 1. The cores I/O pins have different Read more

By [email protected], ago

List of tests for each IO core

I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in a separate file. This post will list down the tests conducted for each device GPIO Write to the control register to set the data direction Write to the data register Read more

By [email protected], ago

IO Cores Automated Test Benches

This post is a documentation of the final version of automated test benches created to verify our IO cores. The test benches have been created for the our GPIO, Master SPI, Slave SPI, UART & I2C master and slave. The test benches verify only the behavior of those devices within their specs. It doesn’t have any random tests or tests for their behavior out of their specs. Here is an overall explanation of how the test benches work First, each Read more

By [email protected], ago

Automated Test Bench Algorithms

In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This is opposing to the normal test benches where a waveform or textual dump of signals is generated and the user has to verify the correctness of the outputs himself. In Read more

By [email protected], ago

Witty on OpenShift

We are considering deploying Witty applications on OpenShift. In theory, it should be possible to do it but it’s still necessary to test things out. There are some unanswered questions on how such a deployment might work. This blog entry was very useful in getting things deployed on a DIY cartridge. However, there are some minor issues that needed to be tweaked. Starting The start action hook that I used was: nohup $OPENSHIFT_REPO_DIR/diy/hello.wt –http-port=$OPENSHIFT_DIY_PORT –http-address=$OPENSHIFT_DIY_IP –docroot=$OPENSHIFT_REPO_DIR/www |& /usr/bin/logshifter -tag hello.wrt Read more

By Shawn, ago

Dear Verilator, Please Shut up!

Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like warnings so I shot them down one by one until Verilator had absolutely nothing to say. This blog explains a couple of tough warnings that I had to figure out on my Read more

By [email protected], ago

Generating 64-bit Hexadecial Numbers with Bash

In order to test my GPIO design whose width can vary from 1 to 64 bits I need to be able to generate random values to properly drive it’s data line. I need a method that’s fast and fairly random as it will run for many repetitions. Before that I’ve used the verilog $random function and it behaves very good when you supply it with a random seed but it’s limit is 32 bits I think. I could have concatenated Read more

By [email protected], ago

Verilator Explained

As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose language errors and any bugs in one of the simulators. Hence, I’ve tried to compile my test bench with Verilator and the process wasn’t as easy as I expected it to be. In this post I’ll give an overview of Verilator focusing on how it’s different from Icarus Verilog. The main difference stems from Read more

By [email protected], ago

GPIO Automated Test Bench

In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test bench for the GPIO over the past week. In this post I’ll explain it’s features and give a block diagram to two ways that can be used to implement this design. The GPIP new automated test bench have the following features:  It’s basic testing sequence is it sets the GPIO direction, writes Read more

By [email protected], ago