The Final Task
This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design. The Final Task Since the last task is to design a Verilog module, which I have not been doing it since the demosaic modules. Just like what I previously done, I drew out the circuitry that I am going to infer on using Verilog, and examine the signals. The design Read more