After doing some reading I managed to find the right SQL. I tested it on PostgreSQL first because that’s how Dr Shawn taught me. He told me before I start working on something I need to know what I want then it will be easy for me to follow the right path. Otherwise all the things that I do will be useless. Next, I have to work with Query Builder in CakePHP. I have to find the right query and Read more
This week did not start off well. Despite spending the weekend trying to get the application to work on the Pi, it still kept on crashing in most parts of the application. This was getting frustrating as it was working on both my computer and the work computers but failed at the actual deployment environment in which we were going to run the application on. When I showed the application to Dr. Shawn on Monday, he noticed that it was Read more
I spent this week measuring the TCP performance of the CORS program. We wanted to know how fast can the board actually perform from a network perspective. I collected data on multiple parameters that I’ve determined to have a considerable impact on speed. I was appalled to find out that the PIC32 was reading data from the network at around 560 Kbit/sec, and after testing, I managed to improve it to 30 Mbit/sec. For my trials I used iperf and Read more
On my first day of internship, Dr Shawn talked me through a git branching model and I proceed to study more on Git for the rest of the day. Then, I spent the following two days studying witty and web application. On the fourth day, Dr Shawn came to the office. After reading through the codes written by the previous interns, Dr Shawn explained the simulator project to me in detail. On the fifth day, I studied about web application Read more
After much reading and some calculations, I learnt that theoretically the ideal bits of the LFSR counter in my design should result in the range of 300 µs to 5 ms debounce time. The width had to be quite large since the FPGA board clock speed was 100 MHz. For validation of the specific time to be put in the design, I tested the push button with a range of LFSR widths. I started with low widths that gives about Read more
With the deadline approaching, I spent the last week making sure that the application is accessible and user-friendly enough for the end user. This was mainly accomplished with the use of CSS. With that done, I continued with deploying the program on the tablets. However, there was an issue with the browser rendering the overflowed portion of a page black when accessed in full screen mode. There was also what initially thought to be a problem with logging in into Read more
This makes my 11th week with Aeste. I started off by implementing the generation of the RNG key which is to be read from the flash and performing even more trials to make sure it works exactly the way I believed it did, which Dr. Shawn stressed. Because most interns including myself half-ass everything 90% of the time, and the code is just yolo. I believe my half-assed implementation worked, but the Flash and FPGA libraries were still full of flaws, and Dr. Shawn notified me Read more
I start this week by working with PostgreSQL which is a new thing for me. I have to learn how to use it first before I start. So basically this week I try to familiarize myself with PostgreSQL and doing some SQL commands to solve fix the bug. But in the end of this week I just realized that I have misunderstood Dr Shawn’s instructions and the way I use PostgreSQL was wrong because I was not using the development Read more
For this week, I work on instantiating the modules. Each signals’ name need to be the same as object’s name. For example, a signal named ‘ack_i’ should have an output like ‘B1_ack_i’ as ‘B1’ is the object name. This is achieved by using substring in an AUTO_TEMPLATE. Then I make sure the necessary information will be successfully captured by the computer. For now, I have each module instantiated and ready to be connected to the computer. To allow communication between Read more
I basically did the text processing part on the first day of this week. By using regex, the program is able to read through a template and output the signals’ name on a Verilog file. But this technique is not suitable as the user has to make sure that the device is compatible with the template. I basically spent most of the time studying JointJS before I get to talk to Dr. Shawn. We realized the problem of reading the Read more