Module by Module

I carried on with the task of designing the modules in Verilog. I had chosen to work on the Infrared Transmitter and Infrared Receiver. This was quite exciting as it was my first time to work on two modules that work together. I already started designing the code for the modules but it could not be synthesized so I checked the designs again.

First, I checked the transmitter design, it only required output so the design was quite straight forward with Wishbone signals and an output that is in the form of Infrared signal from the module. On the other hand, the receiver design works oppositely reading inputs and an LED on the FPGA board was set to light up as an indicator that the module is detecting an Infrared signal. When all the designs were compiled, they were observed in test bench and the program to test the module on the FPGA board was also created.

While synthesizing in Xilinx ISE, it caused errors apparently because there were signals that was assigned to multiple drivers. I was careless assigning the signals when both the design of transmitter and receiver had to be combined and I assigned the signal more than once. Once the designs were all corrected, I loaded the design on FPGA board but the IR Receiver was working inconsistently. I tested the design of receiver, with and without debounce, changed the width of debounce but it was still the same. After reading the documentation of IR Receiver, I think the module’s sensitivity might have been slightly affected to cause it not to detect the IR perfectly sometimes.

I proceeded with designing the large microphone as the next one. I hope it will work alright as the module also have the exact characteristics as the small microphone designed before. Meanwhile, my research went on, some of the plug that I was reading on did not have an official API thus the finding for the best programmable plug available continues..

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