This week, I made a documentation about naming convention. I learned the importance of documentation and communication because it ensures a smooth workflow of project and it helps someone in the future to understand the concept quickly and continue working on it. Other than that, I study wishbone and learn about the signal between Master and Slave. I find out that signals named ‘stb’, and ‘cyc’ control the timing to latch data. I can manipulate these signals to activate different i/o devices. Dr. Shawn also suggested to check how a previous intern did the design in order to gain some inspiration. Besides, I learned to implement a flexible design to allow user input arbitrary name for different objects. Previously, I had to insert some symbols to ensure all the objects having names with same length because I utilized a technique named ‘substring’ in AUTO_TEMPLATE. Dr. Shawn suggested using regex or lisp in template instead. Therefore, I successfully change the design and now it accepts arbitrary object’s name. By using the naming convention, the program will easily determine the address of each modules. Next week, I need to finish up the wiring part and move forward to next challenge.


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