Dr. Shawn would always remind me not to be consumed or lost in the programming language while learning Verilog as it describes the schematic in designing chips and must be approached as such. Treating it like a normal programming language will not be the right way to study Verilogs. This week, I had the valuable opportunity of learning step by step lessons from Dr. Shawn. Firstly, I was exposed on how to read the codes and bringing out the external Read more…
This week I started on integrating the code and finalizing all the functions so that later on I can include them as libraries in my code. I also worked on writing the bit stream on the flash which will be done using a PUT command and also reading it from the flash which is done using a HEAD command in CORS protocol. The RNG and HMAC and HOTP functions are all completed. I have also listed some of the error and Read more…
This week I finished the HOTP function which uses MD5 hashing to generate a 6 digit code. The secret key used for the HOTP is generated in a separate function, using the MPLAB X built in TRNG (true random number generator) library. As for the configuration bitstream, it will be received and directly sent to both the FPGA and the flash. I was also working on hid_keyboard provided by Microchip, the objective is for the PIC32 to act as a Read more…
This week I continued to study further on the topic of Wishbone signals and also communication protocols. I tried creating testbenches for available codes that had been designed to observe the waveform output but failed to compile it because there were errors. Dr. Shawn pointed out that it was due to my lack of understanding on the communication protocols thus I was not able to make the codes correctly or verifying the resultant waveform. Therefore, I had to study the Read more…
It was about time that I finally dealt with all of the bugs (took me long enough) and it’s a good thing that I did, considering how silly and simple the solution for most of them was. I got the feeling that a bunch of them will emerge though once the entire project gets deployed for the client to use, which is on Tuesday, but that’s for the upcoming week, along with all the updates and changes which will need Read more…
This week I was assigned a few tasks by Dr. Shawn. The first one is to familiarize myself with tools such as Emacs and GTKwave. Emacs is a handy text editor which are extensible and can also be customized. Meanwhile, GTKwave is a tool for viewing and analyzing waves. I used both these tools for my Verilog design programs and testbenches. At first, I was quite slow to get myself used to the basic and movement commands in Emacs but Read more…
This week I worked on the HMAC-based one-time password (HOTP) key which is used to encrypt the message. The encryption is achieved using a key and a counter. The HOTP code is based on a work done by one of the previous interns. As Dr. Shawn pointed out, the main problem with HOTP is that it needs to store the key and the counter on the flash memory which will reduce the life expectancy of the memory. The alternative method Read more…
With Monday and Wednesday being public holidays, one could say that this was a pretty short week. Continuing with the tasks from last week, I had most of the work done on Tuesday and Thursday, setting up new pages, enhancing already implemented features, such as the “date picker” and “auto suggest” through the use of JQuery. That leaves me with one more page which I need to set up, along with the bug fixes. I will also have to thoroughly Read more…
Started off this week trying to finish off my work from the previous one, whereas I was making some progress, it wasn’t fast enough and I couldn’t see myself being capable of finishing things off before the deadline, that being, the client meeting. I had managed to set up the search functionality eventually while at home through the use of a CakePHP plugin, but once I had checked in the morning, I saw that Dr. Shawn had already implemented it Read more…
This week I tried solving the problem I was facing with putting the FPGA in configuration mode, which I have also explained in my blog last week. The main issue is that after TCPIP_STACK from Harmony Configurator is initialised, pin D0 will not be configurable anymore. I have tried reading the peripheral selection register for pin D0 (RPD0R), it reads 0000. According to the data sheet, 0000 corresponds to “No Connect”, which means the pin is used as a normal Read more…