Completing the sensor module

This week I was suppose to work with MSPI (Master Serial Pheriperal Interface), however I didn’t manage to complete the sensor module. So I had to continue with it this week. The digital touch sensor I created was incomplete as it is unable to be used like the sensors in Read more

Adding Modules to the Simulator

Last week I have understand the whole project system, so starting from this week I will begin to start my task — Implementing IO modules into the simulator. Dr Shawn advised me to start with the easiest modules, which is the sensor modules. Sensor modules are easier comparing to other Read more

Documentation for Project

This week has been spent mainly on documentation of the previous work that had been done. Simplify Code Documenting the code is reminding myself on why do I write it in the way at the first place. Some of the code often comes with unused variable and function where they Read more

Search for System Bugs

This week, I continued with my previous week task, to find the way on how SPI C code actually work with the Verilog module. I stared on the same circuit for hours, but then I still could not find the way to integrate them together. And finally I decide to Read more

First week at Aeste

This is my first week as an intern in Aeste. Currently I am the only intern here along with two part-timers (who are also ex-interns for Aeste). During my first day, I got scolded for not completing the pre-materials. As a result, I was given a week to finish studying Read more

Analyze the Inferred HDL

This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers, which are the control register and data register. However, these assumption can actually be verified through the circuitry of the core itself. Read more

BRAM Size before Synthesis

This week continues with the issue that I had opened previously, which is on the issue that some file is not updated before the synthesis starts. This was a mistake made by the previous intern, that the ramSize (BRAM size) that is needed for synthesis is never been specified correctly Read more

CodeMirror Code Completion

I finally got an improved version of code completion working. I am glad that there is a working example, which i referred my work on. It was a frustrating process because  there is no explanation on what is actually going on. I spent a great deal of time understanding the Read more