I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream.
To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals below based on the Wishbone specification.
- DAT_I: It denoted the data input array, the size of the array was determined by the port size
- DAT_O: It denoted the data input array, the size of the array was determined by the port size
- ACK_I: It showed the end of a bus cycle of the MASTER
- ADR_O: It denoted the address output of the MASTER
- STB_O: It showed a data transfer cycle of the MASTER
- ACK_O: It showed the end of a bus cycle of the SLAVE
- ADR_I: It denoted the address output of the SLAVE
- STB_I: It showed a data transfer cycle of the SLAVE
I tended to confuse about the signals at the beginning as I misunderstood the wiring of the Wishbone switch. However, after I gained an understanding of all the Wishbone signals, I was able to draw a schematic diagram of the Wishbone switch to determine its inputs and outputs. An example of verilog code was shown below.
input [ADDR_WIDTH-1:0] up_adr_i;
input [DATA_WIDTH-1:0] up_dat_i;
output [DATA_WIDTH-1:0] up_dat_o;
input up_stb_i;
output up_ack_o;
output [ADDR_WIDTH-1:0] down_adr_o;
input [DATA_WIDTH-1:0] down_dat_i;
output [DATA_WIDTH-1:0] down_dat_o;
output down_stb_o;
input down_ack_i;
output [IO_ADDR_WIDTH-1:0] io_adr_o;
input [DATA_WIDTH-1:0] io_dat_i;
output [DATA_WIDTH-1:0] io_dat_o;
output io_stb_o;
input io_ack_i;
Furthermore, I was advised by Dr Shawn to create an equality and a multiplexer.
Before diving into the equality and the multiplexer, one should understand the format of addresses assigned to different I/O devices. An example was shown below.
K3 = 0x40000000;
K4 = 0x40001000;
K5 = 0x40002000;
Considering the equality, it would compare the address of upstream with a parameter and hence it would select either the downstream or the I/O device. Only two bits were required for the comparison.
always@(posedge clk_i) begin
if (up_adr_i[31:30] != PARAM && up_stb_i) begin
down_stb_o <= up_stb_i; // downstream stb goes high
io_stb_o <= ~up_stb_i; // iostream stb goes low
end
else if (up_adr_i[31:30] == PARAM && up_stb_i) begin
io_stb_o <= up_stb_i; // iostream stb goes high
down_stb_o <= ~up_stb_i; // downstream stb goes low
end
end
Considering the multiplexer, it would decide which acknowledge input to pass back to the Wishbone switch.
always@(posedge clk_i) begin
if (down_ack_i) up_ack_o <= down_ack_i;
else if (io_ack_i) up_ack_o <= io_ack_i;
end
It was also possible to design the switch using only wires, but there would be no memory as registers were not implemented. Moreover, it relied entirely on conditional statements. However, it should produce the identical outputs.
assign match_addr = up_adr_i[31:30] == PARAM && up_stb_i;
..
assign down_stb_o = up_stb_i & (~match_addr) ;
assign io_stb_o = up_stb_i & match_addr;
assign up_ack_o = io_ack_i | down_ack_i;
Another way of designing the switch was to use 1 bit of the address for each I/O device, and it could take up to 18 I/O devices as there were 18 bits available in the address. The advantages would be each I/O device could have more than 12 bits of data (except the last one) and the switch could pass the data to the next I/O device by simply shifting 1 bit of the address. However, the total number of I/O devices were only limited to 18 and the address was not standardized.
All in all, I would continue to work on the Wishbone switch and instantiate the switches in a cascading fashion.
0 Comments