The Xilinx Synthesis and Implementation
As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, this link also provide further detail on these processes. The implementation process is the one with the UCF file to be incorporated with, where it is a continuation from the synthesis process. As long as the Verilog modules did not change, synthesis can be skipped by using the same synthesized output file and run with the new implementation.
I had modified some of the code, in order to make the automated synthesis and generation of bitstream. I started to work on the code editor part because it would be the primary step for the user to generate new modules. The generation of bitstream actually takes few steps and it usually takes a few minutes to do so. It is not practical to generate the bitstream again and again everytime the user modify the code. Thus, my task is to rerun the synthesis and implementation only if the user modify/create their modules in the code editor.
As I got advice from my supervisor previously, I tried not to add more code, but to understand the code first and modify some part of it. This actually keep the code simpler and cleaner.
A Way of Debugging on Group Project
The debugging of the code is painful, especially on a project where many people are working together with. Logging could be very useful in such case, especially when there is a logging of message started with the name of the function. For example : Function1: Error at phase 2;
This actually ease the debugging process and saves A LOT of time. It would be annoying especially when there is a mix of logging methods. For example:
Log1: Function1: Error at phase 2.
Log2: Error here.
How does one actually know where the Log2 function belongs to? And each file may be 1000 lines or more. Of course, a grep command can be used to locate it, but it might not be easy to locate when the message is a common word. Especially in the case that the code is not written by you, it is definitely a nightmare when you grep a log message that is a common word.
Anyway, my next task is to automate the generation of bitstream if the user change the schematic editor without user intervention.
That’s all from me this week. Happy Lunar New Year to everyone!!! 😀
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