I2C core

I2C is the last IO device going into our system, for now.

I2C is more complicated than both UART and SPI. It’s complication is due to it’s ability to have many masters and slaves on the same bus. Moreover, having only one bidirectional line(SDA)  for data transfer adds to it’s design complexity.

The latest specification for I2C from NXP should be your main source for learning about I2C. I2c online guides like this and this can be very helpful. While they tend to use the same figures from the specification there is always some extra explanation and FAQ that’s helpful for I2C beginners.

Now that we have learned about I2C it’s time to refer other designs for hints and inspiration. FPGA4fun is a nice place to start with it’s over simplified explanation and simple implementation. However, for a higher quality coding and more powerful designs you can find few implementations on open cores. This is my favourite one.

Now I have to get back to reality and discuss my own design. My device is based on a single FSM. Wishbone write cycles are used to create the signals for triggering the  FSM and set various flags that determine reading, writing or end of transfer. A clock divider is used to create a clock that’s five times that of the I2C SCL frequency. Another counter is used to count those five cycles that construct the SCL pulse and trigger various events of the SCL and SDA lines.

Currently the design is missing the acknowledge signal which is expected to add more complications.

The I2C slave is still untouched but now that the master is almost over my understanding of I2C has levelled up. I plan for my slave to be using few edge detectors and hopefully try my best not to use a FSM. Moreover, I need to improve the performance of AEMB after I removed its instruction cache and finally create an SOC that can accommodate up to 8 accelerators.

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