In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more…
This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Read more…
I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on the project by going through one by one from the basics to the complicated process of Read more…
The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, Read more…
This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM to delay the signal, when it is extremely large cycle to be delayed with. My supervisor Read more…
Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 Read more…
This week I was assigned to draw the schematic for the demosaicing algorithm. The algorithm is separated into two parts, which is bilinear interpolation in the boundary of image, and PPG interpolation for the rest of image pixels. The Overview of Demosaicing Schematic The hardware implementation of the demosaicing requires Read more…
This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that Read more…
I am officially in the midst of my internship now, and decided to try something new to me, which is chip design. I was given the tools of Atyls Spartan 6 FPGA development board for the development of chip design. The Xilinx ISE tool There are many documentations provided by Read more…
This week I have started working on initializing the block ram (BRAM) with some content. There are so many ways to initialize your memory with. You can for example directly initialize it form your HDL code. But this way is inefficient and tiresome as you have to keep changing your Read more…