This week I was assigned to draw the schematic for the demosaicing algorithm. The algorithm is separated into two parts, which is bilinear interpolation in the boundary of image, and PPG interpolation for the rest of image pixels. The Overview of Demosaicing Schematic The hardware implementation of the demosaicing requires Read more…
This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that Read more…
I am officially in the midst of my internship now, and decided to try something new to me, which is chip design. I was given the tools of Atyls Spartan 6 FPGA development board for the development of chip design. The Xilinx ISE tool There are many documentations provided by Read more…
This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: Read more…
Progressing from where I stopped last week, this week I had to finish everything up and make sure that everything works as it’s supposed to. Before I go in details and describe what I have done, I have to clear some stuff that were left from last week up regarding Read more…
In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools and concepts. In next paragraphs I’ll try to summarize what I have learned so far .. So let us get started ! Read more…
Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun 😀 Read more…
In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and Read more…
In this week I had to continue working in creating Verilog top level module . As I mentioned in my last blog entry, the top level module should contain modules such as: processor, switch and several IOs devices. The instantiation of these modules was completed successfully in last weeks. In Read more…
This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror with witty to extracting the user objects IDs (Check out my previous blog entries for more information ). This week the task Read more…