This week is one which is solely focused on Witty and it has been a rather interesting one because it is the one that I started realizing the great power that it comes with. I would still say that my understanding of it is just a mere scratch as the Read more…
Witty is a very large library that consist of different specific function a good web application will need. In this week I tested some of the function and try to create very simple function, like an application form of sorts. The structure of code in Witty is very different from Read more…
This first week of internship in AESTE has been a unique experience as I am already being prepared to do some real application. Firstly , learning Wt does comes with its own perks and also downsides. It is a relatively new web toolkit with its stable release only last year Read more…
By today, I have finished my first week at AESTE Works (M) Sdn Bhd. My name is Islam Abdalla and I’ve finished my third year in Universiti Teknologi PETRONAS, studying electrical and electronic engineering. Before starting here, I didn’t know exactly what to expect. The interview were somewhat technical, and Read more…
The journey of the 8 months internship has just begun in this week. The first day I had a warm welcoming and introduction of the project that I am assigned to. This moment was really priceless, because I really had been waiting for it for a long time. The Read more…
This post is a documentation of the final version of automated test benches created to verify our IO cores. The test benches have been created for the our GPIO, Master SPI, Slave SPI, UART & I2C master and slave. The test benches verify only the behavior of those devices within Read more…
I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in Read more…
The ultimate future goal is to create a generic Automated Test Bench that can be used with any of our IO cores. Of course the test vectors testing each core has to be different. However, since all our cores use wishbone bus this simplifies creating a generic solution. In this Read more…
In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This Read more…
Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like Read more…