Engineering Elegance

Environment Variables for Xilinx tools

Last week I created a script to run all Xilinx tools required for implementation from the command line. We are using the 14.4 version of Xilinx software. Before using any of the tools in this version a Xilinx script is required to be executed to set required environment variables. However the script sets variables for many Xilinx tools such as Vivado and Plan ahead that are not necessary for our process. Hence, this week I had to dig through Xilinx Read more

By [email protected], ago

MASTER & SLAVE Modes

My next task was to do something to make the PIC able to switch between the MASTER mode and the SLAVE mode. Generally, the MASTER mode will be the mode where the PIC will be acting as a server and will be receiving the bitstream from the Internet and then save the bitstream into the SD card, while the SLAVE mode will be the mode where the PIC will be reading the bitstream from the SD card and send the Read more

By chewjiaxien, ago

Redesigning the Base64 Decoder and more about SD cards

This week was a real eye opener in many ways. Physically I was unwell, and mentally I was fatigued. But it throughout the week, I picked up a lot of advice from the supervisor and I hope I was able to implement some of them in my work this week. Bitstream Header File The first task of the week was to look at what was learned from the research done on the Bitstream Header File. As explained previously, the Bitstream Read more

By [email protected], ago

Interacting with the Compiler

this week was a very frustrating one, full of mysteries and brain teasers… I spent the first few days trying to get the compiler to compile some error code,and get the error message . The challenge was without using shell commands. This lasted for a day or more before I figured it out, but at the end I ended up using shell commands as the code I produce was very risky and may crush the my application. After that , Read more

By ademi, ago

Prototype SOC completed

The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive. First of all the SOC is complete. I have tested various modular switches differing in the number of devices each accommodates. I have tested switches that can accommodate numbers of devices starting from 2 devices all the way to Read more

By [email protected], ago

Detailed look at bitstreams, and a taste of Base64 and SD card CRC

Much of the week was spent trying to find out as much as possible about the Xilinx bitstream file formats (.bit). The actual configuration within a bitstream file is encrypted and is not available for public use. The FPGA usually contains the encryption key to be able to run the .bit file and configure itself. So the following information was gather regarding bitstreams, and some of the interesting features about the bitstreams. What is a Xilinx Bitstream? The full internal Read more

By [email protected], ago

Real Work Begins

After tuns and tuns of reading, my supervisor gave me  the green light to start working on my part , the web Interface. in this week, My main task was to implement the Ace editore using C++ webtool kit into the editor web page . With the help of  webtool kit and ace documents, I managed to finish this task the very first day! However all my problems started at that point. The next step was to manage to get Read more

By ademi, ago

Base64-Encoded CRC16-Included Uploading

Last week, I was only able to verify that the CRC16 feature in the SD card is working. The data will only be written into the SD card when the CRC16 given is correct. If the CRC16 isn’t correct, the SD card will not contain the data in the respective sector and a CRC error will be returned from the SD card and the writing process cannot be continued. The CRC is hardcoded within the code to send the same Read more

By chewjiaxien, ago

System on Chip

Compared to my work the title might be a little too fancy but hopefully our switches will evolve from simple switches to a smart interconnect between the processor and all other system components. Do you remember the second version of the accelerator switch I talked about in my previous blog post? It turned out it’s not a good choice. The reason is that in my implementation I inferred a tri-state buffer inside the design. However, tri-states should only be connected Read more

By [email protected], ago

How big is thy Bitstream?

It was an up and down week of sorts. It didn’t start off but as the week wore on and with some crucial help/advice from the supervisor and colleague, the desired task was achieved, although it is yet to see if it was the best solution to the problem at hand. One important aspect of problem solving that was picked up during the week was the fact that the objective must be clear to be able to solve any problems. Read more

By [email protected], ago