Engineering Elegance

Application Modifications

The functionality of the Inkscape extensions was almost finished last week. Most of the work I’ve done this week was optimization and modification to different parts of the application. Some of these changes were made to the Witty application (in C++) and some were made to the extensions (in Python). Import extension The first of these changes was applying the new naming convention for naming the pins of the elements. I explained the naming convention we implemented first in my Read more

By [email protected], ago

ISA Size Comparison

Just to do a quick and dirty comparison of several popular ISAs, I compiled a simple C application that calculates primes using the Sieve of Eratosthenes using the following command: gcc -O2 -c -o prime.o prime.c Then, I compared the output binaries just on memory size using the ELF size command. I used the ARM and THUMB outputs as a benchmark for comparison. $ size prime.arm text data bss dec hex filename 244 0 0 244 f4 prime.arm $ size Read more

By Shawn, ago

Free ISA

While work has been under way on our new processor core, which shall remain multi-threaded using interleaved multi-threading in hardware, we have been searching for a free ISA to use as the base instruction set. Our previous microprocessor was based on the Microblaze instruction set (ISA). While there is nothing inherently wrong with this architecture, it seems to have lost some allure and stagnated for a while. So, I was recently reminded of RISC-V, an ISA that was released last year Read more

By Shawn, ago

Finishing Inkscape Extensions

I continued working on the the Inkscape extensions that I started last week. I worked on improving and modifying some of the functions of the extensions to make the process of creating components graphics easier. But before that, we had to design and establish a naming convention for naming the components and their pins. Previously for our tests we created simple components manually, and thus we chose temporally names. However, now we are automatically generating an entire library, thus we Read more

By [email protected], ago

Extracting I/Os Addresses

In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and wiring between them. If you are following my blog entries you will notice that I have encountered some issues with the switch module as we had two routes to take,  Read more

By [email protected], ago

Application Tweaks

Last week I spent most of my time studying the application and try to solve the application problem. Let us first go into the problems that I have discover in the application first. revoking the certificate twice This event is highly unlikely to occur, but there is a thin chance of it happening. Previously I used the email address of the user to store their certificate in the approot. In the revoke directory of approot, I have also used the Read more

By [email protected], ago

File system and SSL

This week I focused my study on the various file system to find out the limit of number of certificate that this application can hold. So I first started to search the Internet for the NTFS(New Technology File System) which is developed by Microsft. The quality that I am interested to study from this system is the maximum memory that a file can hold, and the maximum number of sub folder that a folder can have. Then I went to Read more

By [email protected], ago

Creating Inkscape Extensions

My task currently is to generate the graphics library for the components that we are going to use in our schematic editor. To be more precise, it is not my objective to create all the graphics for more than a thousand components, but rather find a way to automate and simplify this process as mush as possible and thus, it will not necessary be me who is going to generate that actual graphics. The method we started experimenting with is Read more

By [email protected], ago

Cascading Switches

In this week I had to continue working in creating Verilog top level module . As I mentioned in my last blog entry, the top level module should contain modules such as: processor, switch and several IOs devices. The instantiation of these modules was completed successfully in last weeks. In this week my work was mainly dedicated to the switch module. The switch is a module that is used -as widely known- to select one IO device to be connected Read more

By [email protected], ago

Wishbone Bus Interface

In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire these instance modules together using the WISHBONE bus interface. The first question came to my mind was “What is the wishbone interface”?. Wishbone is a flexible design methodology used for Read more

By [email protected], ago