I made a mistake when I was integrating the simulator’s functionalities into the other project. I got the wrong idea for testing the simulator but luckily Dr. Shawn corrected me and he taught me where to start with. After I have added some files and separated the back-end and front-end, I decided to commit the changes and push it to the develop branch. When I check the logs before I push the changes, I realized that the latest commits were Read more
This week I managed to finish off the REST API except for the REST client specific specifications which at that time was still undecided. Hence, I proceeded with adding the SMTP functionalities. It took me a while to decide on the best way to take into account the possibility of an email not being successfully sent to its recipient until Dr. Shawn told me that it was somewhat unreliable to predict success anyway so that was a bit of effort Read more
I generally receive a stunned look when I tell people that we build everything with C++ where possible, including web applications. It happened again recently and they will usually ask me – Why?!!! I’d like to document some reasons why we chose to use C++ to build web applications here. I shall preface by saying that we will use whatever language that the client specifies for client projects. However, for our own internal projects we prefer C++ over everything else. Read more
This week, I finished connecting each module to CPU via a customizable switch. I learned the importance of flexibility in design while I was designing the naming convention for different modules and their signal’s name. Other than creating a working design, I make sure the design is elegant and simple. Also, I recorded the technique I used in Wiki on Github to ensure the next intern will understand it clearly. Next, I will be working on generating a UCF file. Read more
This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made a program to extract information from generated Verilog file, so that the naming of pins from Json side matches with the naming on Verilog side. But this causes the program to be unstable as the timing of generating file could be simultaneous. Therefore, I redesign the Read more
I continued to work on the large microphone only to find it was not working. It was weird as it has same characteristics as the small microphone and the design worked on the small microphone. I tried to change the width of the debouncer and tried a design without debouncer as well but it still did not work. Dr. Shawn pointed out if it might be a speaker, producing sounds instead of detecting sounds. Hence, I executed the buzzer design Read more
After a long holiday I am back in the office. This week I only work for 2 days and I only made a little progress with the bug. Right now I still working with the View file and on Friday Dr.Shawn asked me to check 3 things after I told him that I still having problem with the View file. Here the 3 things : Verify that the SQL generated by CakePHP actually retrieves the results Verify that the results Read more
This week, my first task is to check if the simulator simulates the c++ codes correctly. Hence, I referred to the console and looked for evidence to prove it. However, I could not find enough information about the instructions at each cycle in the console. I had to use objdump to display more information about the object code and then look the instruction numbers up. With the help of the RISC-V handbook, I was able to show that the simulator Read more
I finally started coding out the REST API. There was not much to be noted though as it was just mainly implementing the details of what was previously drafted into code. This time I spent a bit more time to plan out the code to reduce copy-pasting code by separating them into reusable modules and also by maintaining some consistency when writing the code which led to a somewhat cleaner codebase compared to the previous application. There was also an Read more
I carried on with the task of designing the modules in Verilog. I had chosen to work on the Infrared Transmitter and Infrared Receiver. This was quite exciting as it was my first time to work on two modules that work together. I already started designing the code for the modules but it could not be synthesized so I checked the designs again. First, I checked the transmitter design, it only required output so the design was quite straight forward Read more