Chronicles from our peeps.
Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun 😀 Read more…
This week I focus my attention on troubleshooting the problem of the application. As I explained in the previous post of the week, there is a few problems in the application and I have found some solution to solve this problems. Decode signal not exposed in Http Client I refereed Read more…
The functionality of the Inkscape extensions was almost finished last week. Most of the work I’ve done this week was optimization and modification to different parts of the application. Some of these changes were made to the Witty application (in C++) and some were made to the extensions (in Python). Read more…
I continued working on the the Inkscape extensions that I started last week. I worked on improving and modifying some of the functions of the extensions to make the process of creating components graphics easier. But before that, we had to design and establish a naming convention for naming the Read more…
In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and Read more…
Last week I spent most of my time studying the application and try to solve the application problem. Let us first go into the problems that I have discover in the application first. revoking the certificate twice This event is highly unlikely to occur, but there is a thin chance Read more…
This week I focused my study on the various file system to find out the limit of number of certificate that this application can hold. So I first started to search the Internet for the NTFS(New Technology File System) which is developed by Microsft. The quality that I am interested Read more…
My task currently is to generate the graphics library for the components that we are going to use in our schematic editor. To be more precise, it is not my objective to create all the graphics for more than a thousand components, but rather find a way to automate and Read more…
In this week I had to continue working in creating Verilog top level module . As I mentioned in my last blog entry, the top level module should contain modules such as: processor, switch and several IOs devices. The instantiation of these modules was completed successfully in last weeks. In Read more…
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire Read more…