The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive. First of all the SOC is complete. I have Read more…
Compared to my work the title might be a little too fancy but hopefully our switches will evolve from simple switches to a smart interconnect between the processor and all other system components. Do you remember the second version of the accelerator switch I talked about in my previous blog Read more…
The I2C core made a lot of progress this week. While I was hoping last week not to use a FSM in my slave I couldn’t resist the temptation. My slave have a FSM and is almost 95% ready. The hardest part is the acknowledge part. Not only that the Read more…
I2C is the last IO device going into our system, for now. I2C is more complicated than both UART and SPI. It’s complication is due to it’s ability to have many masters and slaves on the same bus. Moreover, having only one bidirectional line(SDA) for data transfer adds to it’s Read more…
This week had a lot of testing going. First of all UART is 90% done. It has been tested by simulation and on FPGA communicating with the PC through Minicom. I’ve faced a very interesting issue while testing UART on Spartan 6 ATLYS board. My UART can transmit data to Read more…
This week I’ve finished the second version of SPI. I basically adjusted the formatting of the code to be more professional, easier to read and interpret and better commented. My guide is the code for AEMB, it’s formatting, nomenclature and comments. I’ve come across a bug in SPI. Apparantely the Read more…
This week we have managed to get an SOC that connects AEMB to SHA1 accelerator and a GPIO. Having only one device at each bus of the AEMB doesn’t require much effort in terms of SOC. The software that we used for testing contained our driver for SHA1. Our demo Read more…
I’ve managed to completely remove the Icache from AEMB. Simulation and FPGA implementation were both a success. However, after the edits AEMB now runs slower because it has to fetch each and every one of it’s instructions through at least two Wishbone cycles. It’s worth mentioning that Before removing the Read more…
My new task is to remove the Icache module from AEMB. Basically Icache holds all instructions before execution by the core. Icache acquires the instructions from whatever is holding them externally and keeps them for processing. Icache controls the Instructions WB interface through the ich_hit signal. When the processor needs Read more…
The above blinking LEDs are not regular blinking LEDs. These LEDs are connected to the output of a GPIO. That GPIO is controlled by the AEMB2 microprocessor and the AEMB2 microprocessor is fetching it’s instructions from a 16K block RAM that has been loaded with data using the DATA2MEM software. Read more…