This week we have managed to get an SOC that connects AEMB to SHA1 accelerator and a GPIO. Having only one device at each bus of the AEMB doesn’t require much effort in terms of SOC. The software that we used for testing contained our driver for SHA1. Our demo program runs SHA1 to produce the hash of “abc” and then we display it on LEDs connected to the GPIO. The above video shows the expected first word of the hash value “a9993e36” and shows the LEDs displaying it one byte at a time.
Moreover the GPIO used is the second version of the GPIO created by my colleague enhanced and cleaned by myself.
At this point I’m starting to see the big picture of the whole system.
Since I’ll be cleaning up and writing the second version of the rest of the IO devices that we created so far in this post and the coming ones I’ll post some guidelines about creating efficient Verilog coding that functions properly and is easily understood by others.
Guidelines to good Verilog codes:
1- Think of hardware and schematics while writing your code.
This is the most precious lesson you’ll ever learn about HDL. It’s very important to begin your design by a digital circuit or even better a rough block diagram schematic by hand. When you are coding, always keep in mind what device your code is inferring. If necessary refer to language templates for your Synthesis tools to know the various pieces of codes and their inference targets.
2- Name your signals according to convention.
Refer to other professional codes for such conventions or in case of following a certain architecture refer to it. when writing a hardware tool to perform a mathematical operation you should name your signals according to the variable names conventions. If you are creating signals with no reference try your best to choose a name that involves common sense and can easily help others guess the use of this signal before digging into your code.
3- Comment your code clearly and don’t worry about over commenting it, just explain it as much as your time allows it and enough for others to understand your design.
More guidelines next week, when I learn them 😀