Second Week: Wishbone SOC

For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I Read more…

First week

My First day started with introducing the workplace and the project I’ll be working on followed by a quick introduction about Verilog and the necessary tools that I need to use to do my work. For this week the goal will be to wrap up all the learning that I Read more…