This week, I worked on the schematic of BRAM buffer and demosaic algorithm core. As I going deeper into the design, I found that I had lack of some necessary information, such as how to handle the signal of the demosaic core output later, and how would the demosaic core Read more…
This week, I worked on the design of the circuitry for the demosaic IP core. On previous week, my supervisor and I has come to a conclusion of the usage on HQLI algorithm, as it is more hardware friendly and the result is satisfying as well. The design of the Read more…
Propagation Delay This week, my supervisor had some discussion with me. The first problems was my timing circuits. Previously, I actually made the timing signals by altering the clock edge, controlling the flip flop using the logic circuits into the clock input. However, this is a serious problem to the Read more…
This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that describes the circuit I drew. Initially, I started to rely on Icarus Verilog Simulator, which turns out that the output waveform is Read more…
This week is pretty interesting, as I was working on the timing signals for the CCD. In order to perform demosaicing, my supervisor advised me to understand on the operation of the CCD. The CCD Phase Signal The CCD sensor will only operate and controlled by the timing signals that Read more…
This week I was assigned to draw the schematic for the demosaicing algorithm. The algorithm is separated into two parts, which is bilinear interpolation in the boundary of image, and PPG interpolation for the rest of image pixels. The Overview of Demosaicing Schematic The hardware implementation of the demosaicing requires Read more…
This week, I spent my time to understand and test the demosaicing algorithms in C. Finding the Right Algorithm I had done a lot of searching through the Internet, try to figure out what is the best algorithm to be used, and implement it in C program so that I Read more…
This week, I had been spending time searching on way to test the demosaic algorithm. I did a misunderstanding on previous week, that there is a process between the image sensor output and raw image. The Raw image is directly the output from the image sensor output itself. Well, I could Read more…
This week, I have to choose which area of chip design that I am going to involved in, and I decided to work on the accelerator for chip design. I had chosen to work on the accelerator for Image Sensor, to accelerate the image sensor output into a raw image Read more…
This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that Read more…