Working in Aeste Works is a unique experience that you rarely get in anywhere else. The task here is rather challenging and learning curve is never flat. I have definitely learnt a lot of skills from Aeste. Starting from a knowing-C-only student, I get to learn building a web application Read more…
I learned the way of testing a specific function in a program which is built with REST API. Basically every function is assigned to be accessed with either one of four commands (GET, POST, PUT, DELETE). By using CURL command, I can access and test the functionality of a particular Read more…
This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Read more…
This week, I finished connecting each module to CPU via a customizable switch. I learned the importance of flexibility in design while I was designing the naming convention for different modules and their signal’s name. Other than creating a working design, I make sure the design is elegant and simple. Read more…
This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made a program to extract information from generated Verilog file, so that the naming of pins from Read more…
This week, I made a documentation about naming convention. I learned the importance of documentation and communication because it ensures a smooth workflow of project and it helps someone in the future to understand the concept quickly and continue working on it. Other than that, I study wishbone and learn Read more…
For this week, I work on instantiating the modules. Each signals’ name need to be the same as object’s name. For example, a signal named ‘ack_i’ should have an output like ‘B1_ack_i’ as ‘B1’ is the object name. This is achieved by using substring in an AUTO_TEMPLATE. Then I make Read more…
I basically did the text processing part on the first day of this week. By using regex, the program is able to read through a template and output the signals’ name on a Verilog file. But this technique is not suitable as the user has to make sure that the Read more…
I work on generating Verilog version of source code based on user input which is coded in C++ this week. I study Verilog-mode and the way of this tool functions to properly instantiate the signals’ name. I make sure the program labels each device respectively to user’s input while doing Read more…
On the first day, another intern and I met Dr. Shawn in the office. He directed us to setup some tools for the office usage and he also gave us a talk about the concept of gitflow. Just like every other intern, Dr. Shawn treated us a lunch at the Read more…