I work on generating Verilog version of source code based on user input which is coded in C++ this week. I study Verilog-mode and the way of this tool functions to properly instantiate the signals’ name. I make sure the program labels each device respectively to user’s input while doing the translation from C++ to Verilog in order to organize the system and it also helps when I need to come out with a naming convention for the connection between devices and the board in the coming days.

I was encouraged to use regex for text processing as it would simplify and organize the code. Also, Dr. Shawn introduced a powerful tool named “Jointjs” to me because I will need to use this library to work on naming convention for the connections after I am done with my current task. Dr. Shawn showcased some of the library’s powerful abilities to me. I am impressed and can’t wait to learn to implement this tool on the company’s project.

I would have to spend some time next week to learn about Jointjs. Hopefully, I will finish the translation as soon as possible and get started working with it. In short, a week well spent because I get to learn many new things and I look forward to exploring more in the future.



Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.