My main task for this week was to get the workflow for the web application up and running, and as the title would indicate, that didn’t turn out so well as there were plenty of flaws within my implementation of the required functionalities. I had the workflow sketched out and Read more…
This week I got the wolfssl_tcpip code from Micro-chip running. This code establishes a HTTP server which can then be accessed. My task was to strip away all the extra codes in order to simplify the program. The code is base on Microchip’s code and uses some of the included Read more…
This is my first week as an intern engineer here at Aeste Works. On the first day I was introduced to the project on which I am to work on in full details, once that was covered, I was given a specific task related to the project to work on Read more…
I started the week by generating the BOM and also all the Gerber files needed for manufacturing of the board. Something I learned was if there are any fill areas in the design, it has to be filled before generating the Gerber files. The Gerber files are generated based on Read more…
Routing the board was finished last week. However, the ethernet connection looked really messy and not optimized, Ethernet connections were where I started this PCB design with. Therefore, I rotated the chip and reconnected it again, this time with a lot more care. The connection is now much better. BOM Read more…
This week I was mostly double checking all the connections and also all the footprints. There were a few footprints that needed to be modified and rerouted. The I/O ports connected to the FPGA were also rerouted, this time using the differential tracks instead of single ones. That opens up Read more…