The FPGA is now configurable using the pic32mz. The cause of the problem was identified as being the clock to the FPGA not being set, and also the ucf file declared an unconnected pin, J13 as the clock pin. The problem was solved by enabling REFCLKOx in the Harmony Configurator, System Services->Clock->Use Clock System Seervice?->Clock Configurator Settings->Enable Reference Clock x, and then routing the pic32mz pin to the actual clock pin on the FPGA, and changing the declaration of the location of the clock pin in the ucf file. All REFCLKOx can be used except REFCLKO1 which has been occupied by another device.
Another pin used is the reset pin which is also not set. If the reset pin is in a high state, it will hold the first digital pin in a high state until the reset pin is set low. When the pin is in a ground state the digital pins will proceed to be toggled in the manner defined in the verilog file. In this case I set the reset pin which is also connected to the appropriate pin on the pic32mz and also to an external reset pin. Settting the pin to an open drain configuration will ground the pin whereas input pullup will set it high. In this case it is set to open drain but can be modified if necessary.