This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design.
The Final Task
Since the last task is to design a Verilog module, which I have not been doing it since the demosaic modules. Just like what I previously done, I drew out the circuitry that I am going to infer on using Verilog, and examine the signals. The design this time is merely simple ring counters, which is to show ring counter patterns.
Ring counter is basically made of shift registers, where the detail can be viewed in wikipedia. The implementation is easy and simple, where an always block in Verilog can infer it completely. The tricky part of the implementation is for the inout of the Verilog module, where the inout variable can never be a register. Thus, a simple solution is to assign the inout variable to a register, instead of writing the inout variable as register.
inout [3:0] gpio;
reg [3:0] gpio_reg;
assign gpio = gpio_reg;
Thanks to my colleague Alex that provide me the necessary information for the implementation, I have completed the wiring for the Verilog module. The module is used to test the SD card using PIC32, where PIC32 would be the master and SD card would be the slave. I tried my best to use the same Verilog variable name that had been used by the other projects, so that comparison later can be made easier.
Besides, even for the synthesis, I tried to use the same name for all the files and processes. I tried my best to document every single bit that I could, and I think it would be easier for someone taking over the part later.
Well, I guess that’s all from me. I really appreciate for everything that AESTE has brought to me. It is sad that I could not witness the product to be released. But I enjoyed the moment working with AESTE, the flexibility and the privilege of this part time work is no where can be found.
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