While work has been under way on our new processor core, which shall remain multi-threaded using interleaved multi-threading in hardware, we have been searching for a free ISA to use as the base instruction set. Our previous microprocessor was based on the Microblaze instruction set (ISA). While there is nothing inherently wrong with this architecture, it seems to have lost some allure and stagnated for a while.
So, I was recently reminded of RISC-V, an ISA that was released last year from Berkeley, which was intended to be a free (as in from being encumbered) ISA meant for educational and research use. However, the RISC-V people have chosen not to release a Verilog implementation for it. They have their reasons for doing so but we do standardise on Verilog here.
That does not prove to be a problem as the processor is DLX-like and sufficiently similar to the AEMB in terms of architecture that it is easy enough to adopt for use.
In addition, we have also been searching for a 16-bit instruction set for use in our deeply-embedded version of the new processor core. While the RISC-V has not yet included formal support for a compressed instruction set, work is already moving in this direction and they do plan to include it in the future. Hence, this seems a better bet than sticking with the old ISA.
Therefore, it would seem that we will be basing our new instruction set off the RISC-V ISA while retaining our own hardware architecture. We plan to release two variants of the new processor: a 32-bit ISA one for general applications use and a 16-bit ISA one for deeply-embedded use (once the ISA is ready).
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