Tagged: riscv

Creating an IO object in Javascript 0

Creating an IO object in Javascript

Creating an IO object After nearly giving up and getting some hints from Dr. Shawn, I finally achieved my small task. As I am working on a virtual processor in Javascript, I am required...

A Whole New World 0

A Whole New World

Hi everyone, I’ve just started my work as an Intern Engineer in AESTE and today marks the fourth day which I have spent in this company. For the next 15 weeks (if I’m still...

Memory Map of RISC-V Angel 0

Memory Map of RISC-V Angel

As my colleague started to modify the linker script, I found more problems to be solved in the simulator. The RISC-V Angel Memory One of my concern this week is to set or limit...

Timer Interrupt using RISC-V 0

Timer Interrupt using RISC-V

This week, I worked on the implementation of Timer Interrupt using the RISC-V Angel. The RISC-V Angel had a timer interrupt code for itself for the usage of Linux ELF file. However, it does...

Bare Metal RISC-V Angel Simulator 0

Bare Metal RISC-V Angel Simulator

This week, I finally get the RISC-V Angel Simulator to run the C/C++ code compiled from the default RISC-V GNU compiler, which is specifically designed to compile files into ELF file that to be...

A Deeper Look on RISC-V Angel 0

A Deeper Look on RISC-V Angel

This week, I had really a hard time with RISC-V Angel. It started with finding the bootloader code from the RISC-V Proxy Kernel, as the bootloader is the primary program/codes that needs to be load...

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Instruction Set Architecture

RISC-V instruction set architecture (ISA) is designed to support computer architecture research and education, and completely free for academia and industry use. By using the reference of RISCV-Angel, which is running with the RV64 (64-bit)...

ISA Size Comparison 0

ISA Size Comparison

Just to do a quick and dirty comparison of several popular ISAs, I compiled a simple C application that calculates primes using the Sieve of Eratosthenes using the following command: gcc -O2 -c -o...

Free ISA 0

Free ISA

While work has been under way on our new processor core, which shall remain multi-threaded using interleaved multi-threading in hardware, we have been searching for a free ISA to use as the base instruction...