List of tests for each IO core

I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in a separate file. This post will list down the tests conducted for each device

1. GPIO
   • Write to the control register to set the data direction
   • Write to the data register and to the external circuit driving the GPIO pins
   • Read the data register
   • Read the control register
   • Those tests are repeated through the various possible sizes of GPIO ranging from 1 to 64 bits.
2. Master SPI & Slave SPI
   • Write to the Data register to initiate transaction
   • Keep on reading the status register for a fixed while, this gives time for the SPI transfer to take place
   • Read the data register
   • Read the status register
   • Those tests are repeated for the 4 possible modes of SPI
3. UART
   • Write to the data register
   • Read the status register for a fixed time
   • Read the data register
   • Read the status register
   • Those tests are repeated through all possible sizes of UART Byte (5,6,7 or 8)  and different parity schemes (N,O,E,M,S) and Stop bit length (1 or 2)
4. I2C Master & Slave
   • The I2C master and slave are connected together in the test bench as it requires acknowledgment from slave through all of it’s transactions
   • Slave address is written to the master control register
   • Data is written to the Master data register
   • Status register is read for some fixed time
   • Data register of the master is read.

Those are all the details about the new automated test benches. In the final post I’ll explain the issues that need to be addressed to be able to create one generic device that works with all cores.