ISA and Dependencies
In this post I’ll continue the in detailed overview of the ISA of AEMB where I’ll review memory access, GET/PUT, special purpose register and program flow instructions. Next I‘ll explain about the data dependencies and how they are currently handled in AEMB.
First, there are 12 instructions responsible for memory access. Half of them are load instructions that read data from memory and write it back to the destination register. The data read can be a word, half a word or a byte. The memory address can be calculated by adding two register together or a register and an immediate value. The store instructions write data from a register to the memory and they come with the same options as the load instructions.
Second are the GET/PUT instructions which are used in AEMB to communicate with the accelerators bus. AEMB only uses the blocking instructions which freeze the pipeline until a transaction is complete with the accelerator and doesn’t put a limit on the number of cycles that this takes. Those instructions specify the address of the accelerator to be read as an immediate value and they have a bit to specify whether the register targeted at the device is a control/status or data register.
There exists 4 special purpose registers. Those are Program Counter (PC), Machine Status Register (MSR) and two more registers that contain the exception status and address (ESR & EAR). While all 4 registers can be read, only the MSR can be edited through an instruction. There exists three instructions to write to the MSR, one copies the content of the register to it and the other two set or clear bits from the MSR lower half depending on the values of an immediate value. One instruction exists to read any of the 4 special purpose registers and store their content into the destination register.
Program flow instructions are the family of instructions in the AEMB. 24 instructions exist for conditional branching, 12 for unconditional branching and 4 instructions for returning. Conditional branching compares the contents of register A against zero. All comparison variations exist. There is equal to zero, not equal, greater than or less than, greater than and equal to zero or less than and equal. The address is calculated by adding either the content of register or an immediate value to the current PC value. Moreover, all conditional instructions have an option to include a delay slot after them.
Unconditional branching comes in a combination of options. First, there is the option to branch and link where the content of the current PC is first copied to a register before branching. Second the option exists as to whether the branch target should be an increment of PC or an absolute value. Finally like conditional branches, the presence of a delay slot is also an option. One special branch instruction is a break instruction which manipulate the break in progress bit in the MSR.
Return instructions all calculate the value of the target address by adding an immediate to the contents of a register. However, the difference between the 4 instructions is in the way they manipulate the bits of the MSR. There exists return from exception, interrupt, break or subroutine.
Data dependencies are handled through forwarding and bubble insertion when forwarding is not possible. Since AEMB is a three stage pipeline, it is worth mentioning that data dependencies can only exist between back to back instructions i.e. an instruction can only depend on the instruction right before it.
There are instructions which don’t write back to the register and hence their following instructions can never have a data dependence on them. Those instructions are conditional branches, unconditional branches except when a link is required, return instructions, store instructions, PUT instructions, move to special purpose register and the immediate instruction.
Adding to that, there are three instructions that don’t access the registry file and hence can’t depend on their previous instructions. Those are the GET instructions, move from special purpose register and finally the immediate instruction.
There are instructions that have a latency of 2 cycles and hence can’t accommodate forwarding. Those are multiplication, barrel shifting, LOAD and GET instructions and move from special purpose register. When these instructions are followed by an instruction that depends on them a bubble is inserted in the pipeline by not allowing a write back to the register file and the depending instruction is loaded once more into the pipeline to give the preceding instruction a chance to retire.
Thus forwarding in AEMB is done only with arithmetic, logical and shift instructions i.e. instructions that go through the ALU and have a latency of only one cycle which is enough to forward their data to the following instruction before they reach the execution stage.