# AEMB ISA, in detail

Finally work on the AEMB is to be continued after a long unjustified break. In previous posts I have touched a bit on the Instruction Set Architecture (ISA) of AEMB and explained it’s relation with Microblaze ISA. In order to change the threading model of AEMB to coarse grained, I was warned that after doing the change, some data hazards will become unresolved. This is because in the current AEMB, data dependencies of back to back instructions are being resolved by changing threads after each instruction. Hence, I’ve decided to list down all possible data dependencies before doing the change. Doing that required knowing everything about the ISA in detail. In this post I will give a full detailed review about the AEMB ISA.

Before diving into ISA, two side notes are due. First, a warning to people using the Microblaze EDK-6.3 reference guide. There is a few mistakes that I spotted in the guide in the ISA sections. Luckily all those mistakes were corrected in the latest version of the guide. Hence, if something doesn’t sound right while you are reading those sections simply refer to the latest version.

The second note is about the behaviour of the carry bit in the MSR of AEMB during shift instructions. Supposedly, the carry bit should take in the right most bit shifted out of the operand. However, as I have explained in a previous post, the flag used for this situation (fSHIFT) is not set during shift instructions. The following picture shows an instruction from the AEMB demo program. The instruction in hex is 90A50001 and it denotes SRA $5,$5. As can be seen from the picture, the flag kept a low value and the carry flag remained unchanged. I am not sure whether this is a mistake or one of the aspects where AEMB is different from Microblaze.

Now let’s get serious and talk ISA. First, arithmetic and logical instructions. Addition and subtraction can be carried by 16 instruction each of which giving the user a special choice of options. Subtraction is done by adding the 2’s complement of operand A to the other operand. The operands can be either two registers or a register and an immediate value provided by the instruction. Furthermore, the instructions have the option to add the value of the carry bit into the operation. An interesting ability is to keep the current carry flag unaltered. If the K bit is set, the carry bit is not altered by the operation otherwise, the carry bit receives the carry out value. An interesting compare instruction exists that subtracts operand A from B and then sets the MSB of the destination register if operand A is bigger than B or clears it otherwise. There exists two variations of this compare instruction, one can consider A & B to be signed numbers and the other considers them unsigned numbers.

AEMB can perform 4 logical instructions; OR, AND, XOR and AND Complement. 8 instructions exist for those logical operations; 4 of which take in two registers as operands and the other four use one register and an immediate value.

As for shifting, 3 variations exist for a right shift. Basically operand A is shifted to the right and place into the destination register. The carry bit of the MSR takes the value of the bit shifted out of A. The variations of shifting defines the value of the MSB in the destination register. A logical shift clears this bit while an arithmetic shift extends the MSB of A into the MSB of the destination. Finally, a carry shift will place the carry bit into the MSB.

AEMB has two Sign Extend instructions, it can extend either a Byte or half a word of one register and place it in another. Barrel shifting has 6 different instructions. The instructions can shift to the right or to the left by a quantity specified in operand B or immediately in the instruction. Shifting can be logical or arithmetic similar to the shift instruction. However arithmetic shifting is only an option when shifting to the right. As for multiplication, two instructions allow multiplication of a register with a register or an immediate value. The value stored in the destination register is the lower word of the multiplication result. Multiplication and Barrel shifting are the only arithmetic instructions that take more than 2 cycles to execute.

Currently, AEMB has two hardware calculation units equipped by choice. Those are a barrel shifter and a multiplier. The mb-g++ compiler used to compile code for AEMB knows of the existence of these units through options passed to it when compiling. While there exists division instructions in the microblaze, AEMB doesn’t have a hardware division unit at the moment and hence division is done in software. Same goes for floating point calculations. Compiler is aware of those settings through it’s compiling options as well.

In the next post, I’ll explain the rest of the instructions left which are memory access instructions, accelerator bus access instructions(GET/PUT) instructions dealing with special purpose registers and program flow instructions. Moreover, I’ll list down the possible data dependencies between instructions.

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