AEMB Data Interface, Execution and Branching

The journey of analysing AEMB is finally reaching a destination. In this post I will discuss AEMB’s interface with the data memory and with the accelerator bus. Moreover, I will explain the design of the execution unit and highlight some of it’s parts that I can’t comprehend yet. Finally I will describe the Branch Condition Checker (BRCC) unit.

The Data interface module is responsible for handling the wishbone communication with the data memory. It issues all the wishbone signals and handles all wishbone timing issues. The AEMB communicates with the data memory only on load and store instructions. Unlike the instruction interface, the data interface utilizes the WB_SEL signal properly and uses it to determine the meaningful bytes on the transferred word. The Accelerator interface module operates the same way as the data interface except that it always sends 4 significant bytes per word.

The execution unit contains an integer unit, a multiplier and a barrel shifter. The integer unit handles addition, subtraction, logical operations and one bit shifting either logically or arithmetically. The execution unit considers any floating point instruction as an exception. Moreover, the integer unit contains the Machine Status Register (MSR). A major difference between the MSR of AEMB and the MicroBlaze is that bit 29 of AEMB MSR contains the current threading phase.

I would like to highlight some of the flags involved in setting the MSR which I don’t understand yet. AEMB uses two flags each for branching to and returning from interrupts, breaks and exceptions.

• The Branch to interrupt flag is set upon a condition where the Opcode is 6’o56 and Ra=01101. However, in the MB instructions, there exists no instruction with this description.
  I think I need to better understand how AEMB detects and handles interrupts.
• A similar situation exists for the branch and return from exception flags where I can’t find a Microblaze instruction with the conditions to set these flags.

• The shift flag is used to load the MSR carry bit with it’s proper value. However, it appears to me that this flag has been configured to be set on sign extend instruction which according to the MB datasheet shouldn’t affect the carry flag.

The Branch condition checker unit, BRCC, analyses the different kinds of branches and determines the result of conditional branches that are calculated in the Integer unit.

To sum up, now that the analysis of distinct modules of AEMB has been concluded, I believe an eagle view of the AEMB is necessary to fully grasp it’s functionality. This needs to be done fast to make up for my slow progress so far.