Unfortunately this week has been the least productive for me. In this post, I will summarize my small progress for this week. More importantly, as the blog title suggests, I will post images of AEMB design that I drew during my analysis. I hope this can make up for my slow progress.
Do you remember the flags which I couldn’t comprehend from last week? It turns out that the conditions for setting those flags does exist when the processor encounters an interrupt or an exception. When this happens, AEMB doesn’t supply the instruction from the instruction memory to the pipeline. Instead, it supplies a certain vector for the case of the interrupt and another for the case of exception. This is the reason why I couldn’t find corresponding Opcodes in the MicroBlaze data sheet.
I now have an almost complete grasp of the AEMB and I am ready to change the threading model and start the characterization. However there still exists a few questions which I haven’t answered. First I still can’t see the big picture of how the processor behaves on interrupts and exceptions. Second, I am yet to completely visualize how AEMB handles data dependencies.
Finally, here is an example circuit diagram for AEMB.