Screenshot from 2013-10-18 14_40_19
Finalizing I2C continues. Finally the master is fully functioning but tested only through simulation.

Here is the Features of the master:

  • Clock Synchronization and Arbitration.
  • Detection of a busy bus.
  • Supports Arbitration loss.
  • Handles Slave induced waits.
  • Capable of repeated start and back to back reads and writes.

Future Improvements:

  • Add support for Various I2C speeds
  • Add support for special I2C addresses
  • Solve the drawn back of the master losing arbitration if the required slave is not present

The master is triggered through Wishbone write Cycles:

  • READ starts when an address ending with 1(read) is written into the Address register.
  • WRITE CYCLES start when data is written to the data Buffer and an address ending with 0 (write) is written to address register.


  • Order of writing address and data doesn’t matter but the cycle will commence only when both have been written.
  • If data is written and then a read address is supplied the master will commence a read cycle and ignore the previously written data.
  • After the data is being written the master will commence the cycle only if the bus is not being used by another master. If the bus is busy, the master will wait for the other devices to give away their arbitration then it’ll start the transaction.
  • If master loses arbitration it’ll keep the current data until it regains arbitration and transmits it. This is true unless the user writes new data.
  • In any case if no ACK is received the master gives a STOP condition and goes back to idle state. It gives an error status.
  • New data has to be transmitted to the master while it’s writing the current data in order to achieve a back to back transaction.
  • If you write the same address the master will repeat the transaction without a repeated start. If you write a new address the master will do a repeated start.

The slave can accommodate the same features supported by the master.

Categories: Experiential


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