Work on designing the PCB layout continues in earnest. We encounter a few software issues relating to the hardware of the task, which prompt some worried thoughts.

As always, here’s a look back at the previous week. Click here to skip to the conclusion.

Pin Assignments

During design it became apparent that some routing could be done in a more efficient manner if the pins on the Spartan-6 were repositioned. Fortunately, this is possible since the pins on the Spartan-6 FPGA are general I/O pins, except for the few fixed JTAG programming pins and power pins.

Throughout the project, pins were assigned and reassigned. Since some component footprints were repositioned on the board as well, some pins were shifted to a different I/O bank of the Spartan-6 as well. The removal of some digital I/O headers as described last week provided some flexibility for the task.


KiCAD has its own autorouter, but the developer (and many other users) recommend using the autorouter utility from, which can be launched from the menu bar of PCBnew or the website itself. The designer can then export the PCB design from KiCAD as a standard Specctra DSN file which FreeRouting can work on. From then onwards, it is just a one-click autorouting process (with the option to tinker with design rules); the software will generate an initial plot and optimise it under multiple passes.

The existing Spartan-6 design with some manual traces was passed to FreeRouting. Despite multiple iterations, it was found that the failure rate for autorouting remained as high as 50%. On reason was because the autorouter could not interfere with the placement of existing routes and parts. The board area is already very constrained, and there may be no possible way to route every single pin on the netlist.

Solution: Compromise

After hundreds of iterations, the attempt to use the autorouter to finish the board was abandoned. Instead, the rest of the board must be manually routed.

The benefit of manual routing is that the designer can quickly spot how to shift traces and components to widen chokepoints and open new pathways on the board. While tedious, this would be necessary to route the remaining pins while maintaining the existing design decisions for positioning decoupling capfacitors, oscillators, transmission line terminations etc.

Moreover, the designer knows the function & priority of the pins and is capable of making design judgments. By the end of the week, all the core modules of the board were successfully routed (even the optional Bluetooth module!), but there remain a few pins of secondary importance on the PIC18 that cannot be routed. It may become inevitable that some of them remain unused for the end-product.

My initial hope of finishing up the PCB layout by this week was pinned on the autorouter, however the constraints on the board proved to be too much for it. Somehow I expected it to work like a miracle, but even software has its limits.

Regardless, much progress has been made with more than 80% of the board complete, so although work did not go as planned, I expect the PCB to be completed by Monday on the latest. Of course, according to the Pareto principle that final 20% will take up 80% of the total project time, but I have scarcely any time to think about that.

Categories: Experiential


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