Previously, the PIC18 was programmed to emulate 3 separate slave SPI devices – an ADC, a Flash memory and an Ethernet controller! The final task proved to be a notable challenge, and remained only partially implemented by the end of the week.

This episode: there will be a double dosage of Ethernet as we attempt to establish the Data Link layer of the PIC18 and take another look at the physical Ethernet connector on our circuit board! A month ago we started on the schematics and now, 28 days later, more work is still to come as we complete the routing of the Spartan-6 and prepare the board before we begin PCB design.

Click here to fast-forward to the end.

Ethernet Controller

As described last week, the PIC18 has to emulate the ENC28J60, a stand-alone SPI Ethernet controller. There are seven key functions in its SPI instruction set, which deal with mainly reading and writing to the control registers (i.e. ETH, MAC & MII registers) as well as the buffer memory.

The main hurdle to emulation is the different addresses of same registers in the ENC and the PIC18. Fortunately, it was possible to create a mapping function that takes in an ENC address and then translates it (in the geometric sense) to the actual address. There are also a number of unimplemented or reserved registers which need to give a fake response.

Beyond that, the work on code went swimmingly, and all the functions of the SPI instruction set were able to be emulated except for the System Reset Command (SRC), which was not implemented because it would reset the whole PIC18. Figure 1 shows the result of writing to Ethernet transmit buffer via SPI (WBM) and then reading its contents afterwards (RBM).

Week5_1bFig. 1: Reading the Ethernet buffer. After the point at which the initial write command stopped, the buffer was filled with random data.

The final test was to check if the emulation code was sufficient in creating a Data Link (Layer 2 of the OSI model) between the PIC18 and the network. For this assessment, the PIC18 would try to send an Ethernet packet to the workstation computer. As shown in Figure 2, this packet was successfully detected using Wireshark.

Week5_2bFig. 2: Ethernet packets from PIC18

Hardware Schematics

For the remainder of the week, work was focused on the the schematics of the product. The few unused pins of the PIC18 were assigned additional functions such as I/O or LED pins, but the remainder were merely routed to the Spartan-6 for general data transmission purposes. In particular, pins RB4 to RB7 were reserved as interrupt-on-change inputs, also known as “keyboard interrupts”. They would be required to provide a hardware select method for the Spartan-6 to access the features emulated by the PIC18.

Another revision is the ICSP header for the PIC18, which is once again to be combined with the JTAG connector and not the Ethernet port. The previous decision was made because the 10Base-T Ethernet port had four unused pins, which is more than sufficient to allow ICSP programming. However, most Ethernet RJ45 jacks with integrated magnetics terminate the pins internally. In order to proceed, a basic RJ45 jack with separate magnetics or a custom-designed jack, but that would be costly in terms of board area and expenses respectively.

Week5_3Figure 3: Current schematics for Bank 2. (Red for additions, blue for deletions.)

With the slave SPI functions completed, there are still a few more things to consider about the board schematic including the dilemma of what to do with the other 100 or so pins of the Spartan-6. But as the final touches are being applied to the Spartan-6 schematic, we can soon begin working on the PCB design using KiCAD. This has been Lee Kin Wai, signing off.

1 Comment

Week6: Finishing Schematics and PCB Footprints | AESTE · 2013-08-10 at 14:29

[…] from where we left off last week, we make a few last-minute additions to the Spartan-6 schematics and design the footprints of the […]

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