This week i finished up writing the code for the receiver uart. My design includes a transmission register, a state register,  a status register and a few counters. This was the first time, I was using a finite state machine in my design.  My design would wait for a start bit and receive the bits with respect to a count that is a parameter.  When it is time to sample the stop bit, the design would indicate if there was an error if the stop bit was not sent. The user can then either choose to process the data or dispose it.

Right now i am working on implementing it on the spartan 3 board. Wish me Luck!


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