ASH1: Input and Output Ports

ASH1 has 2 output ports and 1 input port whose specifications are like the following:

• Input Port 0 (iport0)

An 8-bit input port with 4 schemes of encoding (table 1):

For NRZL, ASH1 will push/load the status of iport on the stack directly with no specific form of signal shaping. For NRZI, ASH1 will check if there has been a change in the states of all the pins in the port from their previous states. In the case of a change, the corresponding bit pushed/loaded on the stack will be 0. Otherwise, it will be 1.

For differential encoding with NRZI, it can be used for USB operations along with output port 0 (oport0). In this mode, a USB PHY chip must be interfaced to iport with (Rx+,Rx-) connected to iport[7], iport[6] respectively. ASH1, based on Rx lines states, will load the data bit acquired on the top of the stack at the 7^th bit position (i.e. qtop[7]). This implementation was done due to the fact that USB packets are sent with low-order bits first. So loading the bit acquired at the MSB position gives the chance to have the data byte after shifting 8 times to the right. It is important to note that iport[5:0] are of no use during this mode. However, this can be expanded in the future, to include multiple differential pairs with the rest of the iport. There is a flag associated with differential encoding called diff_state (flag2[0]) to indicate a valid differential state or not. This flag must be checked by the program to take the required action.“11” encoding scheme has the same behavior as NRZL with the intention that it can be used for MAC Ethernet signaling.

• Output Port 0 (oport0)

An 8-bit output port with 4 schemes of encoding:

For NRZL, ASH1 will load the oport0 latch with the top of stack element (qtop). The top of stack element can be either POP-ed out or remain unchanged. The same goes for “11” encoding scheme.

For NRZI, ASH1 will change the opor0 latch bit values according to the value of their corresponding bits in the top of stack element (qtop). If it’s 0, the bit will get inverted. Otherwise it will stay the same. The top of stack element can be either POP-ed out or remain unchanged.

For differential encoding with NRZI, it can be used for USB operations along with iport. In this mode, a USB PHY chip must be interfaced with oport0. The Tx+,Tx-, Speed and Output Enable  pins of the USB PHY chip is coupled with opor0[0], oport0[1], oport0[7] and oport0[6] respectively. oport0[6] (enable) will always be 1, while oport0[7] (speed) will depend on the value of the flag (flag0[1]) that is set by ASH1 through srb instruction according to the speed of communication used. oport0[1:0] (Tx-,Tx+) values will be based on the following : top of stack element LSB (qtop[0]) due to the fact that USB protocols send bytes with LSB first.  Bit stuffing will also determine the value of oport0[1:0] through software algorithm (the instruction can specify whether to send the data byte’s LSB or to perform stuffing).  ASH1 will read the states of Rx+, Rx- (iport[7:6]) and based on the bit to be transmitted, it either invert the states of Tx+,Tx- (if the bit is 0) , or keep it the same otherwise. The reason that ASH1 checks Rx+,Rx- is because they are coupled to Tx+,Tx- when iport and opor0 are set for USB operations along with USB PHY chip. An example of USB PHY chip interfacing is shown below

• Output Port 1 (opor1)

An 8-bit output port with 4 schemes of encoding:

For NRZL, ASH1 will load the oport1 latch with the top of stack element (qtop). The top of stack element can be either POP-ed out or remain unchanged. For NRZI, ASH1 will change the opor1 latch bit values according to the value of their corresponding bits in the top of stack element (qtop). If it’s 0, the bit will get inverted. Otherwise it will stay the same. The top of stack element can be either POP-ed out or remain unchanged.

Among the future improvements on the current I/O ports is possibly the ability to synchronize with  specific data rates through the implementation of a phase-locked loop unit in addition to the integration of Ethernet signalling that I am currently working on.