ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals:
| Interfacing with | Signal | Width | Direction/ Type (with respect to ASH1) |
| Master CPU | clk | 1 | i |
| reset | 1 | i | |
| strb_wb | 1 | i | |
| we_wb | 1 | i | |
| ack_wb | 1 | o | |
| data_i_wb | 8 | i | |
| data_o_wb | 8 | o | |
| addr_wb | 8 | i | |
| int_ack | 1 | i | |
| int0 | 1 | i | |
| int1 | 1 | i | |
| int2 | 1 | i | |
| Peripherals (PHY) | iport | 8 | i |
| oport0 | 8 | o | |
| opor1 | 8 | 0 |
Being an IOP, ASH1 needs to communicate with a master CPU that tells ASH1 what to do and what data to be exchanged. ASH1 makes use of a wishbone bus ( which enables various parts of an integrated circuit to communicate with each other). The details for the wishbone bus interface implemented in ASH1 are shown below:
| WISHBONE DATASHEET for ASH1 | ||
| Description | Specification | |
| General Description | 8-bit slave input and output port | |
| Supported Cycles | Salve READ/WRITE | |
| Data Port Size | 8-bit | |
| Data Port Granularity | 8-bit | |
| Data Port, Max Operand Size | 8-bit | |
| Data Transfer Ordering | N/A | |
| Data Transfer Sequencing | Undefined | |
| Signal Name | WISHBONE Equivalent | |
| clk | CLK_I | |
| reset | RST_I | |
| strb_wb | STB_I | |
| we_wb | WE_I | |
| ack_wb | ACK_0 | |
| data_i_wb | DAT_I() | |
| data_o_wb | DATA_O() | |
| addr_wb | ADR_I | |
The data to be exchanged settle down in one of three units:
- Tx FIFO: The data in this buffer is written by the master CPU only and read by ASH1 only.
- Rx FIFO The data in this buffer is written by ASH1 only and read by the master CPU only.
- Register File (dual port access): whose memory cells can be accessed (read/ write) by both ASH1 and the master CPU.
Tx and Rx FIFO buffers require no protocol as the data integrity is safeguarded (read or write is only from one party). However, the register file needs a specific protocol agreed between ASH1 and the master CPU, for instance, ASH1 can read all the registers but write to a specific ones only and the same goes with the master CPU. Nevertheless, if both parties try to write at the same time (at the same location), the priority is given to the master CPU, ASH1 can check this condition by testing the flag (wr_reg, flag0[0]) after a write operation by ASH1. If the flag value is one, then it means that the priority was given to the master CPU access on which a specific action can be taken. It must be noted that this checking must be performed immediately after the access instruction if we suspect that the master CPU is overriding as the flag values will reset upon the next instruction.
A suitable protocol would be that when ASH1 is ready to receive configuration information from the master CPU, it interrupts the CPU to request the configuration information. Within this time, ASH1 will check a specific location in the register file that denotes the completion of configuration loading
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