fpga

This blog post marks the end of my first week in Aeste.  In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I am able to understand the work on Alya’s project as she has concluded her internship. I spent a couple of days just Read more…

I continued to work on the large microphone only to find it was not working. It was weird as it has same characteristics as the small microphone and the design worked on the small microphone. I tried to change the width of the debouncer and tried a design without debouncer Read more…

I carried on with the task of designing the modules in Verilog. I had chosen to work on the Infrared Transmitter and Infrared Receiver. This was quite exciting as it was my first time to work on two modules that work together. I already started designing the code for the Read more…

My work on the passive buzzer had entered its 4th week. I did not like that 4 weeks means a month. When days become weeks, and weeks become a month, you know your work performance is not doing good and you need to do something about it. I wish I Read more…

I thought taking few days off the week would leave me regretting for my work productivity as the time spent would not be enough. However, this week went alright. Well time is never enough of course, but this week was slightly better than some of the weeks before. I paused Read more…

On Monday, I was almost done with the design code for my first module, a 7 colour auto flash LED. I chose this module to start with as it is quite simple to program (only outputs), in the hopes that I can finish it quick.  However, what seem simplest is Read more…