It Has Arrived

This week the board finally arrived and immediately I noticed that the ethernet jack was missing after notifying Dr. Shawn I then started testing the board with an led blink test program and verified the PIC and LEDs are working. I then moved to testing the USB with a simple comport test code to send a string and verified that the USB is connected and working properly. Next step was to test the FPGA, so firstly I tried to put it in the configuration mode by driving PROGRAM_B pin low and wait for INIT_B to follow and then drive PROGRAM_B high and as soon as INIT_B goes high, FPGA is in configuration mode and ready to receive the bitstream. After testing, I verified that the FPGA goes to configuration mode with no problem. However, I failed to successfully configure the FPGA.

PROBLEM/ISSUE

My test program was checking for DONE pin to go high which suggests that the FPGA is configured. The problem was that the DONE pin would not go high. My initial thought was that the DONE pin can not be read by the PIC thus the failure. After playing around with the code and MPLAB configurations, I consulted Dr. Shawn and he suggested a few possibilities that I should work on. At the end the problem turned out to be an incorrectly connected SPI clock. While I was working on the PCB design, I made a mistake of switching around the pins on the FPGA in order to get better layout positions for the tracks and mistakenly connected the SPI clock to a pin other than CCLK on the FPGA.

SOLUTION

Since CCLK is connected to the PIC, Bit-banging can be used to transfer the configuration bitstream. It basically means to mimic the SPI CCLK and Dout using 2 normal GPIO. The data should be transmitted bit by bit. Dr. Shawn suggested a really interesting way of determining the bit value, so this is how it goes, first each byte of data is transmitted to a 8 bit signed variable and then checking for the sign (+ve or -ve) of that variable will determine the last bit in the number and then with a simple left shift, the next bit can be checked. The clock signal also goes from low to high in every transmission. This is certainly a good way around the problem.

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