Creating the Verilog Top Module

This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror with witty to extracting the user objects IDs (Check out my previous blog entries for more information ). This week the task was quite different in term of the language used 😀 . My task was simply to create the verilog top level module from the C++ code . The top level module will contain the instantiation of modules(object that the user defined in the code editor), so before proceeding and discussing more about this topic let me first talk about my verilog experience in general .

I encountered with verilog first time during my college study in Digital Electronics II. I only learned some basics of this language (which was apparently not enough to complete the new task 😀 )  , therefore I had first to revise my knowledge of verilog. Verilog is hardware description language or HDL . A hardware description language is a language used to describe a digital system: for example, a network switch, a microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can describe any (digital) hardware at any level. I really recommend the following pages for a person to start learning verilog from the scratch :

The main building blocks of verilog design are called modules. When you instantiate a module inside another module , the latest is known as higher or the top module. So simply the top level module is a module that contains all the instantiation of lower level modules. So my task was to create the top level module based on the objects the user declared in the editor. Each object in C++ code corresponds to a verilog module. For example if the user declares a “gpio” the code should be able automatically to generate the top level modules containing the instantiation of the “gpio” module. The task was not only to instantiate the corresponding module but also to do the connections and the wiring between different components(modules).

The instantiation of any module is similar to instantiate an object of class in C++ and it follows the following format : 

                                  The module-name   the instance module-name   ((port_connection_list) ).

Each module can have many ports which makes every instantiation of the module very tedious for the verilog programmer. The task is no more tedious with the Emacs Verilog-Mode package that provides the AUTO feature.These features look for /*AUTO*/ comments in the Verilog code (Module definition ), and expand them into the appropriate text. For more information regarding the Emacs Verilog-Mode you can visit the following page:

In conclusion and to sum up what has been accomplished so far, the code is now able to generate a top level module that contains the instantiation of the lower lever modules that correspond to the objects the user declared in the code editors. The Emacs Verilog-Mode AUTO feature was used which made the instantiation of different modules easier and less tedious. Next week I will work in wiring and make the connection between the modules in the top level.

Thanks for reading .. Stay safe 🙂

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