Wildcard DNS

There is one piece of the puzzle that is needed to deploy our new product, that is a wildcard DNS. I had assumed that we would need to…

FPGA now working

The FPGA is now configurable using the pic32mz. The cause of the problem was identified as being the clock to the FPGA not being set, and also the ucf…

Testing the FPGA

Started the week by checking some of the keyboard code to find out what is wrong. I found that the device driver for the keyboard seem to be…

Restructuring keyboard code

This week I restructured the code for the usb keyboard, the aim is to modify as little as possible from the original demo code, so that there is a…

Firmware testing

This week I proceeded to test the firmware created by the previous interns. The first thing I needed to do was replicate their result. One thing I realised…

Switching to actual board

Started the week by continuing on with implementing a hid keyboard on the pic32. While doing this I encountered two major problems, one is that the keyboard refuses…

MPLAB X IDE and Harmony Configurator

This is my second week in Aeste, I was tasked to familiarize my self with MPLAB X and also harmony configurator, especially on USB stack and tcpip stack. For the…

First Week as Intern

Started off my first week as an intern here at AESTE. Before coming here I had less than 2 weeks to study my pre-internship materials, as I had applied…

Clarification on Wt Session Timeout

If you used Wt, you should be aware of the  session timeout set in wt_config.xml. I think this ‘feature’ requires more explanation on it rather than When a session…

Leveraging on WResources

I continued to move all storage related actions to the back-end. The idea is to have a clear separation of front-end (consisting of widgets and callbacks) and back-end…

Final week at Aeste

This week I am still working on the data corruption error when testing the write operations of each modules together. It took me quite a while to find…

Back-end Caching

Caching So.. this week I focused more on building the file caching mechanism that fully uses the server’s back-end. I am using a write-back approach to handle the…

Digging Deeper into Bug

This week I dig deeper into identifying the TCPIP Stack bug. Ideal Case Based on the document UG380 and XAPP502, ‘init_b’ of FPGA should be HIGH (reading from…

Display Data on Schematic

This week I tried to show the data values on the simulator schematic when performing data transmission with UART, MSPI or I2C. When successfully reading or writing data,…

TCPIP Stack Bug

This week I continue trying to figure out how to ‘download’ a huge file with TCP protocol. Set up a USB cdc com port to ease debugging. Fixing…