FreeRTOS Tick and Tick Handling

This post represents the fifth phase of porting FreeRTOS for AEMB processor. The main concern of this phase is to get the FreeRTOS configured to demonstrate the Preemptive Multitasking. By far this phase deals with the following: Setting up the timer to generate the RTOS Tick Handling the RTOS Tick In the previous post, cooperative multitasking was intoduced and successfully demonstrated. However in cooperative multitasking, the interrupt and the interrupt handling had not yet been implemented. As a result, there Read more…

Yick Hong: Introductions

I’m a final year student from Multimedia University (MMU), currently pursuing¬†Bachelor of Engineering (Honours) in Electronics. As for my first post in AESTE’s blog, I’m sharing my experiences on job application to AESTE, and the work progress thus far. The job application to AESTE involved two stages. The first stage is answering screening questions in Google Doc, which covered¬†areas in Processor Architecture, Software Programming, FPGA/ASIC Design, Computer Networking and Web Development. Following this was the phone interview by my supervisor, Read more…

FreeRTOS Cooperative Kernel

In the previous post, I wrote about creating a simple FreeRTOS task. However, to demonstrate the FreeRTOS cooperative kernel, more than one task is needed. Basically when starting the FreeRTOS scheduler, an Idle task is automatically created which is an infinite loop so when the kernel starts running, it will never return back the control to the main program. In cooperative multitasking, it is the responsibility of the currently running task to give up the processor resources to allow other Read more…

Running a FreeRTOS Task

Continuing the series of the posts about my work in porting FreeRTOS for AEMB processor, this represents the third phase of the project which is running a simple FreeRTOS task. In my previous post I mentioned about a problem that I faced during simulating FreeRTOS by using Icarus Verilog. While it has been decided to move on to the next phase of the project with either one of the memory management implementations heap1 or heap2, the problem of the unaligned Read more…

Clustering Icarus Verilog

Icarus Verilog is a popular open-source digital circuit simulator distributed as part of gEDA. While it is a fast simulator, it runs largely single-threaded and does not exploit the modern developments in computing. Depending on the complexity of the circuit involved, a single simulation run can be fairly time consuming. At AESTE, we are using our cluster of workstations to perform parallel simulation runs. While a single simulation run is still time-consuming and it cannot distributed, we can perform N Read more…

Simulating FreeRTOS

In this post, I will explain to you how the simulation of the FreeRTOS kernel was accomplished for AEMB processor. The second phase of porting FreeRTOS for AEMB according to the project plan is simulating the compiled and linked FreeRTOS kernel on top of AEMB hardware. As I mentioned in my previous post, different processor architecture requires different instruction set to communicate with the hardware. Consequently based on the executable file obtained from the successful compiling phase of FreeRTOS for Read more…

Stack Processor Review

As I mentioned in the previous post, the two basic foundations for my project are to get familiar with the stack processor architecture and to know the exact I/O operations. I started with a quest for knowledge about the stack processors. Stack Computers: the new wave by Philip J. Koopman was my first station. This book gives an overview about stack processors, how stacks work and their different structures. Moreover, it presents detailed descriptions for some of the stack processors Read more…

Upgraded Office Plans

Our office plans have been upgraded! This is the new layout of the office plan. Compared to the previous one, there are a few changes. Firstly, the lounge area has been turned into another meeting area. The sofa has been removed. This mini meeting area is particularly suitable for close discussions where people work on a shared piece of paper. There is a TV nearby for presentations. This area is furnished with a small Melltorp (098.682.37) table and Snille (298.750.05) Read more…

Xian Loong: Learning Starts with a Hello World

Hello world! This is my first week working at AESTE. I am very excited to learn and to produce results within twelve weeks of my internship time-frame. I am a final year electrical and electronics engineering undergraduate student from the National University Of Malaysia (Universiti Kebangsaan Malaysia, UKM). I am always interested in how hardware works and the theory behind it. AESTE is perfect for me to explore more of this. I first met my supervisor at a talk he Read more…

Power Debugging

This EETimes article has a good overview on how to do power-debugging. At AESTE, we are working on something similar but for a slightly more sinistre purpose. However, looking at something like this is extremely encouraging as we know that there are others out there working along the same lines and we are not alone. At AESTE, we believe that power is a systems problem that encompasses everything – from the electronics through to the people using the device. Therefore, Read more…