In-Cache Execution Environment

The AEMB is designed with an FPGA target technology implementation. Since this is the case, it may be prudent to exploit certain FPGA capabilities that are not present on ASIC technologies. One such capability is the ability of an FPGA to pre-load the contents of block memories from an FPGA image. This ability is often used to create a read-only RAM block or ROM block. However, if the write-enable signal is enabled this ability can be used to pre-load the Read more…

Conjoining Resources

Since increased concurrency seems like the way to go for computing, I am interested in increasing the concurrency of the AEMB from 2 to 4 hardware threads. This can be done through a dual-core set up. However, I plan to make my dual-core AEMB special by sharing resources between them so that it doesn't actually cost twice the amount of chip resource to implement two cores. So, it is more like having the power of two cores at the cost Read more…

Compiler Futures

At present, all software is compiled using a custom GCC compiler backed by binutils and newlib. However, as the AEMB processor is sufficiently different from the original architecture, it may be time to start porting a new compiler to it. At the moment, the regular GCC compiler is used (with some software hacks) but the architecture can only diverge further in the future. Therefore, steps are underway to build a custom port of a compiler. The leading candidate of choice Read more…

Microkernel Considerations

I have been thinking about implementing some sort of OS on the AEMB. At the moment, the OMRP people have had some success with running a uCLinux OS on the AEMB. However, using uClinux may be a bit excessive for simple projects. Therefore, I have thought of implementing some form of micro-OS on the core. I have already written a simple boot-strap programme that checks the memory for errors. It is a simple programme that can even fit entirely inside Read more…

Kernel Mode

While thinking about the idea of using a micro-kernel, the idea of introducing a special 'kernel mode' came about. However, unlike other processors, this kernel mode does not expose any special instructions. The idea is to switch the instruction execution from external code to internal code. When the processor first boots up, it should start by running the boot-loader, which is located internal to the core. This boot-loader will then run a memory-test routine to ensure that memory is not Read more…

EDK63 Virtual Peripherals

As mentioned earlier, the idea of virtual peripherals is quite tempting on the AEMB core. The two independent hardware threads can be used to implement a single threaded application along with a second thread performing maintenance functions such as interrupt handling. It is therefore possible to implement some hardware peripherals in software. The reason for this idea is the target market of the core. The AEMB is targeted at small and resource efficient FPGA implementations. It is often used in Read more…

Single Precision Aid

While this may not be implemented in the EDK63 version of the AEMB, it is an idea that has been on my mind for quite a while. Software floating-point emulation is expensive in terms of time while hardware FPU is expensive in terms of resources. So, a hybrid method might be useful. A single-precision float may be assisted in hardware by adding some extra functionality. While a full blown FPU will take up too much resources, a simple device that Read more…

EDK63 Mode Activation

There are several methods that can be employed to enable/disable special operating modes of the AEMB. The most obvious method would be to set/clear special bits within the MSR register using the standard instructions. However, there is another method of doing it that may be employed. Firstly, it is possible to use any branch instruction to activate or de-activate any special mode. All branch targets are meant to be word-aligned. Therefore, any non-aligned branch could be used for this purpose. Read more…

EDK63 Thread Independence

The EDK62 core introduced multi-threaded capabilities to the AEMB2 in the form of fine-grained multi-threading using a barrel processor. Essentially, it interleaves and alternates the instructions for the two threads on each clock cycle. However, the two threads are inter-locked, which means that one blocking thread will block the other thread as well. Thread Dislocation This problem reduces the performance of the AEMB2. Therefore, the EDK63 core will unlock the two threads so that one blocking thread does not block Read more…

EDK63 Cache Memory Block

Resource efficiency is always a goal of the AEMB2 design. In order to further reduce resource consumption and improve operating speed, some minor changes are being made in the next generation EDK63 core architecture. The first block to experience some changes is the cache memory block. Looking at the numbers for the EDK62 core, the tag memory block uses 3% (74/2444) of the total core resources. With an additional data cache planned for the EDK63 core, this will increase. Furthermore, Read more…