They say the first week is always the hardest. At the start of my second week, I was supposed to get the computer to read and write into an SD card by programming the PIC18F8722. After being on the receiving end of the massive scolding last week, I was being very fearful of getting it again and I guess the fear really hampered my thoughts and I wasted one day looking completely at the wrong direction in trying to find Read more
This is going to be my first weekly blog post at Aeste! I just joined this company as intern. As for the first week of my internship, Shawn asked me to study Git and do some C programming tutorials just to make sure that my understanding of the C language is decent enough to study the Linux Kernel which will be one of the main tasks during my internship here. Git is a version control tool to keep track of Read more
There were over two hundred applicants for our summer internship places this year. There was a stringent screening process and in the end, we have nine interns for the summer. We have a really good mix of summer interns this year. Our nine interns are working on various aspects of our new product, from chip-design through to web-application development. In terms of alma maters, we have five of whom are studying at some of the top universities in the world Read more
So it has been 2 weeks since the last time I’ve blogged and a lot have happened since then. Today we just finished the design and testing of the SPI peripheral device. That includes an SPI Master and slave that are wishbone compatible and a dummy master to test those two devices. We have tested the design using simulation and by implementing it on 2 FPGA boards connected together through SPI signals. Don’t get too excited reading the above statement Read more
On my fifth week here, I finished up the SPI that was compatible with the Wishbone bus. I was able to have it working for the four modes of the SCLK. I had to make many changes to the design because I did not have the right idea of the SPI’s functionality to begin with. My colleague Mostafa and my boss Shawn took some time to explain to me several issues regarding my MISO and and how similar the four Read more
My first week at AESTE, I was introduced to something that I have never used before which was the new operating system of Ubuntu. Being a complete tyro at it, I was a little puzzled at how this operating system works. I was required to learn about the GIT software which was very useful in the management of source files. Thankfully, a link to the tutorial was given and it greatly helped me in familiarising myself with the new OS. Read more
This lab was really annoying in terms of things that didn’t want to work When trying to export hardware for SDK in PlanAhead error shows [Common 17-49] Internal Data Exception: xps application failed SDK requires gmake, we can solve it by simple linking: cd /usr/bin sudo ln -s make gmake After adding Board Support Package in SDK, it is automatically build. While compiling, error shows /bin/sh: 1: arm-xilinx-eabi-gcc: not found Reinstalling the package like described on this page http://www.wiki.xilinx.com/Install+Xilinx+Tools helps Read more
As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I encountered while going through these tutorials http://www.zedboard.org/course/introduction-zynq as well as their solutions. Proposed solutions are not something new, I didn’t came up with them, this series of posts serves only Read more
After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal number of syllables. Finally, dialogues are not a legit way of communication between modules. Week’s 0010 assignment was to write a wishbone master module that is a part of a Read more
In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. The edge detector was used along with several logic gates to indicate the sampling and shifting of bits according to the mode that is given. The edge detector enables the Read more