Approaching the end of this fourth week I can say that the time for relaxation and learning is long gone and that for doing and developing is nigh. This week was by far the most productive I have had since the start of my internship mainly because I managed to get a small, albeit substantial part, of my project completed. I have designed 1 out of the 5 User Interfaces that are due for submission by mid August and although Read more
For this third week of my internship I had the opportunity to get my hands dirty with coding by writing up my first program for one of the UIs and then testing it out by connecting to a remote PouchDB Database for Data fetching and Data creation. The PouchDB Database can then be synchronized to allow bilateral communication to ensure the client and server both contain the latest states of data. However, the limelight for this last week rests on Read more
During the second week, I worked on my assigned project and also received kind guidance from Dr Shawn whenever I’m stuck. My project involves processing final scores of participants in a competition. This calls for pulling data from a CouchDB database after all the marks by judges are dialed in, or simply after the competition has closed. The Poco library is used. I start by writing some code to fetch data from the server. To do so, I use the Read more
At the start of the internship, I studied Git more in-depth. I appreciate that it will be a valuable tool later on for my projects, such as providing a means of version control. I was given clear briefing about my projects early on by Dr Shawn. My project involves a competition where participants are judged by some judges, and the final award given by a head judge. Thus I am tasked to implement a system whereby I try to reduce Read more
For my second week of internship I started off by completing the design of the PouchDB Database Schema and finalizing its documentation. With some supervision and minor tweaks, I was able to finish up this task at the start of the week. My internship project for these upcoming several weeks revolves around developing an App for one of the projects Aeste has been involved in for the past couple of years. I have been tasked with using the Vue framework Read more
My name is Uzair and I am a third year Electrical and Electronics Engineering student. Today marks the 6th official day since I began my internship at Aeste. Coming from an engineering background, I was given study material that took about 6 weeks to complete prior to the commencement of my internship. Yet still, from my very first day of office, I could tell that I have a long way to go and far too much to learn before I Read more
While there are a lot of examples that describe how to set up a LVM cache on an SSD for a HDD backed storage, they mostly fail to describe an additional step needed to preserve the cache across a reboot on a Ubuntu system. The culprit is that the drivers needed to enable the LVM cache are not built into the kernel, nor available in the initrd. Therefore, these drivers need to be added to the initrd. Additionally, some cache Read more
I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. This week, I have completed integrating the K3rangka with S3padu from the synthesis to bit generation to bram data replacement, writing a function similar to icebram that would replace the hexadecimal contents of the ecp5 bram, and finding a way to initialize the bram contents during synthesis so that the software for the fpga could be Read more
We have been running a thin-client setup in the office for a number of years now as we’ve found them to be easier to maintain, and it allowed everyone to login on any PC and access their work. Our thin-clients were all desktop PC-based machines with Gigabit Ethernet and no storage. However, the machines are getting old (some were close to a decade old) and were starting to show signs of age. So, we had to get some replacements and Read more
This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE flow). All flows are able to retrieve a Verilog file, a constraints file for determining the pinouts of the design, and additional arguments to generate a single bit file ready Read more