Ethernet Operations: An Introduction

As ASH1 is an IOP, it should be able to perform Ethernet operations. In the past days, I have been going through Ethernet references and literature, I must say it’s much more fun than USB. “The diagram … was drawn by Dr. Robert M. Metcalfe in 1976 to present Ethernet … to the National Computer Conference in June of that year. On the drawing are the original terms for describing Ethernet. Since then other terms have come into usage among Read more…

ASH1: Input and Output Ports

ASH1 has 2 output ports and 1 input port whose specifications are like the following: Input Port 0 (iport0) An 8-bit input port with 4 schemes of encoding (table 1): Encoding Scheme Description 00 Non-Return-to-Zero-Level  (NRZL) 01 Non-Return-to-Zero-Inverted (NRZI) 10 Differential Encoding with Non-Return-to-Zero-Inverted (NRZI) 11 (same as 00) – can be modified in the future For NRZL, ASH1 will push/load the status of iport on the stack directly with no specific form of signal shaping. For NRZI, ASH1 will Read more…

ASH1 : Life Cycle

ASH1 is growing and the design is being modified continuously to allow for further flexibility and capability in performing I/O operations. However, these modifications won’t be drastic. ASH1 core is there ! So in the future, there will be slight changes in the instruction set or components. The design flow for ASH1 is shown below: My goal is to see ASH1 post-silicon validated!

ASH1: Communication Protocol

  ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing with Signal Width Direction/ Type (with respect to ASH1) Master CPU clk 1 i reset 1 i strb_wb 1 i we_wb 1 i ack_wb 1 o data_i_wb 8 i data_o_wb 8 o addr_wb 8 i int_ack 1 i int0 1 i int1 1 i int2 1 Read more…

ASH1: An Overview

As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features. Below is the block diagram of ASH1.   It consists of a data stack, a control unit, a program counter, an arithmetic/ logic unit (ALU), a cyclic redundancy checksum (CRC) unit, an input port, two output ports, a wishbone interface unit, a register file, two FIFO buffers, and three flag registers. These components are interconnected among each other via two Read more…

ASH1: CRC Operation

One of ASH1 features is that it can perform – what we can call – software-controlled CRC calculation. As we know CRC incorporates bit shifting, xoring and in sometimes inversion. We decided to have a unit in ASH1 that is dedicated to all these operations. For instance, we want to calculate CRC for a data byte prior to its transmission, we would simply push the byte on the stack, signal the CRC unit to start the calculation and then -without Read more…

Visual Diff

As an open source hardware shop, we have to contend with some serious limitations when it comes to source control tools. However, this person has come up with a way to do visual diffs of circuit schematics and PCBs using existing tools. All the we need to do is to adapt it to our standard processes. Yeay!

ASH1: Another Milestone

It’s always nice to have a meeting at AESTE. It charges you up and gives you the necessary motivation. If you want to get motivated … AESTE should be your destination where you can see ambitious people pursuing their passion.. For the next phase of my work on ash1. It’s planned to work on the following streams in parallel : Documentation : paper work + documenting + coding style. Integration of Ethernet Operations ash1 Assembler Development. regarding future posts, I Read more…

ASH1: A glance at speed and size

Hi again ! As the goal for ash1 is to make it as small and as fast as possible. I’ve tried to investigate the size and speed features of ash1. As we have seen from the previous post, ash1 is pretty small (~500 FPGA slices)… I guess this is super cool if we compare it with a typical MAC Ethernet IP core (~2800 FPGA slices). Moreover, it’s smaller than AEMB processor core (~1500 slices). So in terms of size, the Read more…

ASH1: FPGA proven!

It has been a while since my last blog … I was busy with my exams and university issues  for about a month. So, here we come again to talk about ash1. Since I have started working on ash1, I was anxiously waiting for the day where I can write a piece of code and test it out on an FPGA device and this is what happened ! On 20th of August, 2011, ash1 executed its first program that I Read more…