First Week in Aeste

I am a fresh graduate with Bachelor of Electronics Engineering from Multimedia University Cyberjaya. I found my passion in electronics hardware and programming when I was in secondary school. During that period, my teacher taught me to write a simple program – sending data from PC, and receiving it with a 8051 (via RS232). I was very excited when I saw the system worked well since it was done by me! During my university life, I have participated in ABU Read more…

ASH1 : An LCD Driver and VGA Colour Controller

After integrating Ethernet operations into ASH1.. I though of demonstrating ASH1 as an IOP .. so I looked for a simple I/O operation, yet a simple one to make my life easy when I am writing the code for it in binary. I decided to make ASH1 works as an LCD driver in addition to VGA colour controller. For the LCD driver code, I wrote the code and compared it with the one used in PIC Projects: A Practical Approach Read more…

CRC Operations: A follow-up

Cyclic Redundancy Checksums generation and checking were among the challenging things in implementing ASH1. Looking for the accurate way to calculate/check CRCs took me a lot of time as it was confusing in terms of the following: Bit Orientations (LSB first or MSB first). The Initial Value of the CRC register (0s or 1s). CRC Orientation and Inversion. Through checking some online resources, I found out that it is not only me who faced this problem. People here were struggling Read more…

Ethernet Operations: Random Generator

Back-off is an important feature of the Ethernet MAC protocol. After a collision is detected through the MII/RMII interface, ASH1 should stop transmitting (there are more specific details about when exactly to stop transmission) and then reschedule its retransmission by generating a period of time to wait before retransmission. The period of time is based on a random number chosen by ASH1 and used in its back-off calculations. The amount of total back-off delay is calculated by multiplying the slot Read more…

Ethernet Operations : an eye-opener!

I have mentioned many times that ASH1 should be as small and as fast as possible… The current version of ASH1 is able to perform USB functions pretty good ( more specifically 1.5 Mbps USB operations) and other simple I/O operations. However, getting myself into Ethernet and trying to integrate it into ASH1 lets me see potential chances for  improvement of ASH1. For example: Although, PUSH & POP are frequent operations of a stack-based processor, I designed ASH1 to do Read more…

Ethernet Operations: An Introduction

As ASH1 is an IOP, it should be able to perform Ethernet operations. In the past days, I have been going through Ethernet references and literature, I must say it’s much more fun than USB. “The diagram … was drawn by Dr. Robert M. Metcalfe in 1976 to present Ethernet … to the National Computer Conference in June of that year. On the drawing are the original terms for describing Ethernet. Since then other terms have come into usage among Read more…

ASH1: Input and Output Ports

ASH1 has 2 output ports and 1 input port whose specifications are like the following: Input Port 0 (iport0) An 8-bit input port with 4 schemes of encoding (table 1): Encoding Scheme Description 00 Non-Return-to-Zero-Level  (NRZL) 01 Non-Return-to-Zero-Inverted (NRZI) 10 Differential Encoding with Non-Return-to-Zero-Inverted (NRZI) 11 (same as 00) – can be modified in the future For NRZL, ASH1 will push/load the status of iport on the stack directly with no specific form of signal shaping. For NRZI, ASH1 will Read more…

ASH1 : Life Cycle

ASH1 is growing and the design is being modified continuously to allow for further flexibility and capability in performing I/O operations. However, these modifications won’t be drastic. ASH1 core is there ! So in the future, there will be slight changes in the instruction set or components. The design flow for ASH1 is shown below: My goal is to see ASH1 post-silicon validated!

ASH1: Communication Protocol

  ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing with Signal Width Direction/ Type (with respect to ASH1) Master CPU clk 1 i reset 1 i strb_wb 1 i we_wb 1 i ack_wb 1 o data_i_wb 8 i data_o_wb 8 o addr_wb 8 i int_ack 1 i int0 1 i int1 1 i int2 1 Read more…

ASH1: An Overview

As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features. Below is the block diagram of ASH1.   It consists of a data stack, a control unit, a program counter, an arithmetic/ logic unit (ALU), a cyclic redundancy checksum (CRC) unit, an input port, two output ports, a wishbone interface unit, a register file, two FIFO buffers, and three flag registers. These components are interconnected among each other via two Read more…